EDA技术实用教程课后答案解答_unit5.pdf

0110907班 2009210221 左学 目录 5.7_7人表决器2 5.7_4位4输入最大值检测电路3 5.11 序列发生器4 5.11 序列发生器仿真波形图5 5.138位左移移位寄存器5 5.138位左移移位寄存器仿真波形图6 5.7_7 . 5.7_7人表决器. 55..77__77 .. libraryieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entityvote is port ( seveninput :instd_logic_vector(6downto0); pass_ornot : out std_logic); endentity vote; architecturebhv ofvote is begin process(seveninput ) variableQ:std_logic_vector(6downto 0); begin Q:=0000000; fornin0to6loop if(seveninput(n) =1) then Q:=Q+1; endif; endloop; ifQ4thenpass_ornot=1; elsepass_ornot=0; endif; endprocess; endarchitecturebhv; 0110907班 2009210221 左学 5.7_4 4 . 5.7_4 4 . 位 输入最大值检测电路 55..77__44 44 .. libraryieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entitymaxof4 is port ( input1:instd_logic_vector(3downto0); input2 :instd_logic_vector(3downto 0); input3 :instd_logic_vector(3downto 0); input4 :instd_logic_vector(3downto 0); maxoutput :out std_logic_vector(3downto0) ); endentity maxof4; architecturebhv ofmaxof4 is begin process(input1,input2,input3,input4 ) variabletemp1 :std_logic_vector(3downto0); variabletemp2 :std_logic_vector(3downto0); begin temp1 :=0000; temp2 :=0000; fornin3to0loop