本科论文设计-同步八进制加法计数器版图设计与实现.docx

PAGE \* MERGEFORMATIII同步八进制加法计数器版图设计与实现摘 要21世纪是电子信息产品高速发展的时代。如计算机、手机等电子信息产业的高速发展推动了集成电路产业的快速发展。集成电路电子器件也越来越引起人们越的关注。如手机、电脑中的大规模集成电路也在日常生活中有着广泛的应用。本文首先介绍同步八进制加法器原理图设计，并采用传统的时序逻辑电路的设计方法，列出状态转换表、化简状态方程、由状态方程求出驱动方程、再由驱动方程画出时序逻辑电路等。并介绍基于JK触发器来设计八进制加法计数器的设计和实现方法，并通过HSPICE工具进行了仿真。其次介绍Linux境下CALIBRE工具的使用介绍，并重介绍同步八进制加法计数器版图设计，分析同步八进制加法计数器的组成结构及其工作原理。通过电路图绘制出它的版图，并对它的版图与电路图进行了一致性检测，进一步验证了设计的正确性。本设计对最终设计出的版图使用CALIBRE验证工具进行LVS、DRC及PEX等全面的验证，并顺利通过验证完成最终八进制加法计数器版图设计。关键字：版图设计，计数器，DRC，LVS大连东软信息学院毕业设计（论文） Abstract Synchronization Octal Up Counter Layout design and implementationAbstractThe 20th century is the era of rapid development of the IC, he blooming development of Computer and phone Science has led to the growth of integrated circuit (IC) devices. IC electronic devices also will be attracted more and more attention. Such as mobile phones, computers,most of the Very Large Scale IC applications. This paper first introduces the synchronization octal adder schematic design, the traditional design methods and the use of sequential logic circuits, lists state transition tables, simplifying the equation of state, driven by a state equation, equations, and then draw the equation driven by sequential logic circuits. And describes the design and implementation of the design based on JK flip-flop octal addition to the counter, and simulated by HSPICE tools. Secondly, it introduces the Linux environment using CALIBRE tools introduced and re-introduced synchronous counter octal addition layout design, analysis synchronous counter octal addition the composition structure and working principle. Schematic drawing out through its territory, and its layout and schematics were consistency checking, further validate the correctness of the design.In the end, this design carried LVS and DRC and PEX of verification to the landscape used CALIBRE verification tool that finally designs and passed a verification smoothly. And Validated successfully complete