vhdl设计ad转换状态机.docx

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adread isport(ad_data_in:in std_logic_vector(11 downto 0);reset:in std_logic;clk_50mhz:in std_logic;ad1_eoc_in:in std_logic;ad1_eolc_in:in std_logic;convst:out std_logic;cs:out std_logic;rd:out std_logic;fifo_wr:out std_logic;fifo_cs:out std_logic;fifo_ifclk:out std_logic;fifo_data:out std_logic_vector(15 downto 0);fifo_address:out std_logic_vector(1 downto 0));end adread;architecture art of adread issignal ad_convst_wait_start:std_logic;signal ad_convst_wait_end:std_logic;signal ad_convst_start:std_logic;signal ad_convst_end:std_logic;signal read_ad_state:std_logic_vector(4 downto 0);signal eoc_count_eight_start:std_logic;signal eoc_count_eight_end:std_logic;signal ad_read_start:std_logic;signal ad_read_end:std_logic;signal fifo_tran_start:std_logic;signal fifo_tran_end:std_logic;signal ad_convst_wait_count:std_logic_vector(15 downto 0);signal ad_convst_count_reg:std_logic_vector(2 downto 0);signal ad1_convst:std_logic;signal eoc_count_reg:std_logic_vector(2 downto 0);signal ad1_eoc_reg:std_logic;signal ad_read_clk:std_logic;signal ad_read_data_state:std_logic_vector(4 downto 0);signal ad_read_delay_reg:integer;signal ad1_cs:std_logic:=1;signal ad_data_ch1,ad_data_ch2,ad_data_ch3,ad_data_ch4:std_logic_vector(11 downto 0);signal ad_data_ch5,ad_data_ch6,ad_data_ch7,ad_data_ch8:std_logic_vector(11 downto 0);signal ifclk_reg:std_logic:=1;signal fifo_wr_reg:std_logic:=1;signal fifo_tran_state:std_logic_vector(4 downto 0):=00000;signal fifo_data_reg:std_logic_vector(15 downto 0);beginload1:process(clk_50mhz,reset) begin if(clk_50mhz=1 and clk_50mhzevent) thenif(reset=0) thenad_convst_wait_start=0;ad_convst_start=0;ad_read_start=0;fifo_tran_start=0;read_ad_state=00000;elsecase read_ad_state iswhen 00000=ad_convst_wait_start=0;ad_convst_start=0;ad_read_start=0;fifo_tran_start=0;read_ad_state=00001;when 00001=if(ad_convst_wait_end=1)thenad_convst_wait_start=0;ad_convst_start=1;read_ad_state=0000