[第五章VHDL设计进阶.ppt

图5-11 例5-14的综合结果 control = ‘0’时，X=q; q = ZZZZZZZZ; control = ‘1’时，q =in1; x =ZZZZZZZZ； 5.2.5 双向端口的设计方法 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 5.2.6 三态总线电路设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS port ( input3, input2, input1, input0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END tristate2 ; ARCHITECTURE multiple_drivers OF tristate2 IS BEGIN PROCESS(enable,input3, input2, input1, input0 ) BEGIN IF enable = 00 THEN output = input3 ; ELSE output =(OTHERS = Z); END IF ; IF enable = 01 THEN output = input2 ; ELSE output =(OTHERS = Z); END IF ; IF enable = 10 THEN output = input1 ; ELSE output =(OTHERS = Z); END IF ; IF enable = 11 THEN output = input0 ; ELSE output =(OTHERS = Z); END IF ; END PROCESS; END multiple_drivers; 【例5-15】 对照 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 5.2.6 三态总线电路设计 图5-13 例5-15错误的综合结果 错误的仿真波形图（例5-15 ） Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 5.2.6 三态总线电路设计 library ieee; use ieee.std_logic_1164.all; entity tri is port (ctl : in std_logic_vector(1 downto 0); datain1， datain2，datain3， datain4 : in std_logic_vector(7 downto 0); q : out std_logic_vector(7 downto 0) ); end tri; architecture body_tri of tri is begin q = datain1 when ctl=00 else datain2 when ctl=01 else datain3 when ctl=10 else datain4 when ctl=11 else (others =Z); end body_tri; 【例5-16】 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 正确的仿真波形图（例5-16） 5.2.6 三态总线电路设计 Evaluation only. Created with Aspose.Slides for .NET 3.5