VHDL设计进阶教程.ppt

EDA技术实用教程;;1.2 整数、自然数和正整数数据类型;1.3 4位加法计数器的另一种表达方式;1.3 4位加法计数器的另一种表达方式;1.3 4位加法计数器的另一种表达方式;2 不同工作方式的时序电路设计;2.2 带有复位和时钟使能的10进制计数器;图3 例3的RTL电路;2.3 带有并行置位的移位寄存器;2.3 带有并行置位的移位寄存器;3 数据对象DATA OBJECTS;3 数据对象DATA OBJECTS;3.4 进程中的信号与变量赋值语句;3.4 进程中的信号与变量赋值语句;3.4 进程中的信号与变量赋值语句;【例8】 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DFF3 IS PORT ( CLK,D1 : IN STD_LOGIC ; Q1 : OUT STD_LOGIC); END ; ARCHITECTURE bhv OF DFF3 IS SIGNAL A,B : STD_LOGIC ; BEGIN PROCESS (CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN A = D1; B = A; Q1 =B; END IF; END PROCESS ; END ;;【例9】 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DFF3 IS PORT ( CLK,D1 : IN STD_LOGIC ; Q1 : OUT STD_LOGIC); END ; ARCHITECTURE bhv OF DFF3 IS BEGIN PROCESS (CLK) VARIABLE A,B : STD_LOGIC ; BEGIN IF CLKEVENT AND CLK =1 THEN A:= D1; B := A; Q1 = B; END IF; END PROCESS ; END ;;3.4 进程中的信号与变量赋值语句; 【例10】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE body_mux4 OF mux4 IS signal muxval : integer range 7 downto 0; BEGIN process(i0,i1,i2,i3,a,b) begin muxval = 0; if (a = 1) then muxval = muxval + 1; end if; if (b = 1) then muxval = muxval + 2; end if; case muxval is when 0 = q = i0; when 1 = q = i1; when 2 = q = i2; when 3 = q = i3; when others = null; end case; end process; END body_mux4;; 【例11】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS PORT (i0, i1, i2, i3, a, b : IN STD_LOGIC; q : OUT STD_LOGIC); END mux4; ARCHITECTURE body_mux4 OF mux4 IS BEGIN process(i0,i1,i2,i3,a,b) variable muxval : integer range 7 downto 0; begin muxval := 0; if (a = 1) then muxval := muxval + 1; end if; if (b = 1) then muxval := muxval + 2; end if; case muxval is when 0 = q = i0; when 1 = q = i