νmos-based sorter for arithmetic applicationsνmos-based分类器算法的应用程序.pdf

VLSI DESIGN (C) 2000 OPA (Overseas Publishers Association) N.V. 2000, Vol. 11, No. 2, pp. 129-136 Published by license under Reprints available directly from the publisher the Gordon and Breach Science Photocopying permitted by license only Publishers imprint. Printed in Malaysia. vMOS-based Sorter for Arithmetic Applications* E. RODRGUEZ-VILLEGAS, M. J. AVEDILLO, J. M. QUINTANAt, G. HUERTAS and A. RUEDA Instituto de Microelectr6nica de Sevilla, Centro Nacional de Microelectr6nica, Edif. CICA, Avda. Reina Mercedes s/n, 41012-Sevilla, Spain (Received1 June 1999; In final form 22 November 1999) The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an (8 8)-multiplier and a (15,4) counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using uMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a con- ventional implementation. Keywords: uMOS circuits, threshold logic, sorter cir