基于FPGA多功能频率计的设计.docx

基于FPGA的多功能频率计的设计学生：学号：指导老师：专业：通信工程完成年月：2013年06月（此页封面用统一模板，到时会通知学生）目录摘要3Abstract4第一章绪论51.1 研究背景及意义51.2 论文的研究内容及结构安排5第二章频率测量原理概述72.1 开发平台及FPGA/CPLD简介72.1.1 Quartus II简介72.1.2 FPGA/CPLD简介72.2 数字频率计工作原理概述82.3 测频方法及误差分析102.3.1 常用测频方案102.3.2 等精度测频原理112.3.3 误差分析122.4 本章小结13第三章等精度频率计的系统设计与功能仿真143.1 系统的总体设计143.2 信号源模块163.2.1 预分频163.2.2 分频模块173.3 按键控制模块193.4 测频控制信号模块203.5 锁存器213.6 计数器模块223.7 周期模块233.8 显示模块263.8.1 数据选择器263.8.2 数码管显示驱动263.9 本章小结27第四章总体设计验证28第五章总结与展望30致谢31参考文献32附录文献翻译33英文文献133英文文献237译文1 频率调制39译文2 振幅键控43摘要数字频率计是一种基本的测量仪器。本设计根据等精度的测量原理进行设计，克服了传统的频率计的测量精度随被测信号频率的变动而改变的缺点。等精度的测量方法在具有较高测量精度的同时，在整个频率区域保持有恒定的测试精度。本文论述了利用FPGA/CPLD进行频率测量技术，设计了一个8位数字显示的等精度频率计。它采用Verilog/VHDL硬件描述语言编写程序，在Quartus II软件开发集成环境下进行仿真，包括设计输入、编译、软件仿真、下载和硬件仿真等全过程。软件设计模块分为被测信号、频率测量、周期测量、数码管显示共四个模块。硬件采用Altera公司的Cyclone II开发板EP2C8Q208C8N，系统时钟为50MHZ，该频率计的频率测量范围为15HZ-10MHZ。经过仿真下载验证,能够实现等精度测频率和周期的功能，证明该设计方案切实可行。关键词：数字频率计，FPGA/CPLD，Verilog/VHDL语言AbstractDigital Frequency Meter is a basic measuring instrument. According to the principle of equal precision measurement， this design overcomes the shortcomings of the traditional frequency meter measurement, whose accuracy changes with the measured signal frequency. Methods such as precision measurements with its high accuracy, while the entire frequency region to maintain a constant precision.This article discusses frequency measurement technology using FPGA / CPLD, and completes the design of an 8-bit digital precision frequency meter. It based on Verilog / VHDL description of a programming language under QuartusⅡ simulation environment. It is divided into four modules: the measured signal, frequency measurement, period measurement, digital display. Hardware design uses the development board EP2C8Q208C8N manufactured by Alteras Cyclone II. Its system clock is 50MHZ. This frequency meter’s frequency measurement ranges from 15HZ to 10MHZ. This design includes the whole process of input, compilation, software simulation, downloads, and hardware simulation. Precis