A Study on Impact of Leakage Current on Dynamic Power.pdf

A Study on Impact of Leakage Current on Dynamic Power Ashesh Rastogi, Kunal Ganeshpure and Sandip Kundu Electrical and Computer Engineering, University of Massachusetts at Amherst {arastogi, kganeshp, kundu}@ Abstract — Scaling of CMOS technologies has led to dramatic Studies on estimation of gate, sub-threshold and band-to-band increase in sub-threshold, gate and reverse biased junction tunneling leakage at both gate and circuit levels have been reported in band-to-band-tunneling (BTBT) leakage. Leakage current has literature. Mukhopadhyay et al presented a compact model for now become comparable to the switching current. Traditionally, estimating BTBT and total leakage dynamic power and leakage power are computed separately. current in logic gates such as INVERTER, NAND and NOR gates Dynamic power computation does not include leakage from non- [2]. Brown et al [4] reported an efficient technique for estimating gate switching nodes. In this paper, we show that in upcoming 45nm leakage current by performing a logic state-based analysis of the technology, leakage from non-switching nodes can account for as transistors. Previously, these techniques have not been applied for much as 38% of total dynamic current. Hence leakage from non- estimating leakage alongside dynamic power computation. switching nodes can not be neglected during dynamic power computation. To facilitate this study on large benchmark circuits Our goal in this paper is to investigate h