eda 课程设计 VHDL语言 数字时钟 电子琴---来自重庆大学电子信息工程.doc

rjy4600_cnt60_1—60进制计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity rjy4600_cnt60_1 is port(clk:in std_logic; en:in std_logic; bcd10,bcd1:buffer std_logic_vector(3 downto 0); preset:in std_logic; co:out std_logic); end rjy4600_cnt60_1; architecture rtl of rjy4600_cnt60_1 is signal co_1:std_logic; begin process(clk,preset) begin if preset=0 then bcd1=0000; else if clkevent and clk=1 then if en=1 then if bcd1=1001 then bcd1=0000; else bcd1=bcd1+1; end if; else if bcd1=0000 then bcd1=1001; else bcd1=bcd1-1; end if; end if; end if; end if; end process; process(clk,preset,bcd1) begin if preset=0 then bcd10=0000; co_1=0; else if clk=1 and clkevent then if en=1 then if bcd1=1000 and bcd10=0101 then co_1=1; elsif bcd1=1001 and bcd10=0101 then bcd10=0000; co_1=0; elsif bcd1=1001 then bcd10=bcd10+1; co_1=0; end if; else if bcd1=0001 and bcd10=0000 then co_1=0; elsif bcd1=0000 and bcd10=0000 then bcd10=0101; co_1=1; elsif bcd1=0000 then bcd10=bcd10-1; co_1=0; else co_1=0; end if; end if; end if; end if; end process; co=not co_1; end rtl; rjy4600_cnt24：—24进制计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity rjy4600_cnt24 is port(clk:in std_logic; en:in std_logic; bcd10,bcd1:buffer std_logic_vector(3 downto 0)); end rjy4600_cnt24; architecture rtl of rjy4600_cnt24 is begin process(clk) begin if clkevent and clk=1 then