数字设计基础 双语教学版 教学课件 作者 英Barry Wilknson 双语课件（第10章）.ppt

* 10. Behavioral and Structural Descriptions 10.1 An example 10.2 The dataflow description 10.3 Structural VHDL 10.4 Processes 10.5 Sequential and concurrent VHDL 10.1 An example Example: a Four-bit adder sum = x + y; Describe a 4-bit adder in VHDL 1 1 1 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 Carry out Sum Carry in y x 10.1 An example Circuit diagram 10.2 The dataflow description a behavioral description of the full adder LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY fulladd IS PORT ( x, y, cin: IN STD_LOGIC; sum, cout: OUT STD_LOGIC); END ENTITY fulladd; ARCHITECTURE simple OF fulladd IS BEGIN sum = cin XOR x XOR y; cout = ( x AND y ) OR ( cin AND x ) OR ( y AND cin ); END ARCHITECTURE simple; 10.2 The dataflow description 1. Local signals Full adder circuit with the internal nodes n1, n2, n3, n4 are the internal nodes of the circuit 10.2 The dataflow description ARCHITECTURE number3 OF fulladd IS SIGNAL n1, n2, n3, n4: STD_LOGIC; BEGIN n1 = x XOR y; sum = cin XOR n1; n2 = x AND y; n3 = cin AND x; n4 = y AND cin; cout = n2 OR n3 OR n4; END ARCHITECTURE number3; the VHDL description is changed to Local signals n1, n2, n3 and n4 as part of the description 10.2 The dataflow description 2. Concurrent processing ARCHITECTURE number3 OF fulladd IS SIGNAL n1, n2, n3, n4: STD_LOGIC; BEGIN n1 = x XOR y; sum = cin XOR n1; n2 = x AND y; n3 = cin AND x; n4 = y AND cin; cout = n2 OR n3 OR n4; END ARCHITECTURE number3; Let’s Consider the two descriptions （1） 10.2 The dataflow description ARCHITECTURE number4 OF fulladd IS SIGNAL n1, n2, n3, n4: STD_LOGIC; BEGIN sum = cin XOR n1; cout = n2 OR n3 OR n4; n1 = x XOR y; n2 = x AND y; n3 = cin AND x; n4 = y AND cin; END ARCHITECTURE number4; （2） 10.2 The dataflow description Although they are written in a different order, they do exactly the same t