序列检测与状态机.docx

序列检测与状态机FSM(Finite State Machine/Finite State Automata)，无限状态机，同步状态机，异步状态机两段式：状态切换用时序逻辑，次态输出和信号输出用组合逻辑。三段式：状态切换用时序逻辑，次态输出用组合逻辑，信号输出用时序逻辑。Moore型状态机：次态=f(现状，输入)，输出=f（现状）；Mealy型状态机：次态=f(现状，输入)，输出=f(现状，输入)；混合状态机；Moore型对输入的响应速度滞后一个周期，但输出对输入信号噪声的免疫能力强Moore型状态机的输出信号是直接由状态寄存器译码得到，而Mealy型状态机则是以现时的输入信号结合即将变成次态的现态，编码成输出信号。三段式序列检测10010module seqdet(din,clk,rst,dout);input din;????//输入input clk;input rst;output dout;??//输出reg dout;reg [4:0] CS;??//现态寄存器reg [4:0] NS;??//次态寄存器parameter [4:0] IDLE = 5b00000,??//独热码??????????????????A??= 5b00001,??????????????????B??= 5b00010,??????????????????C??= 5b00100,??????????????????D??= 5b01000,??????????????????E??= 5b10000;always @ (posedge clk or negedge rst)??if (!rst)????CS = IDLE;??else????CS = NS ;always @ ( CS or din )begin???NS = 5bx;???case ( CS )??????IDLE: if (din == 1 )???????????????NS = A;????????????else NS = IDLE;?????????A: if (din == 0 )???????????????NS = B;????????????else??NS = A;?????????B: if (din == 0 )???????????????NS = C;????????????else??NS = A;??????????????C: if (din == 1 )???????????????NS = D;????????????else??NS = IDLE;?????????D: if (din == 0 )???????????????NS = E;????????????else??NS = A;????????????E: if (din == 0 )???????????????NS = C;????????????else??NS = A;???????????????default: NS = IDLE;???endcase?endalways @ ( posedge clk or negedge rst)???if (!rst)???????dout = 1b0;???else???????begin??????????dout=1b0;?????????case (NS)???????????????????????//注意是次态??????????IDLE: dout=1b0;??????????A:????dout=1b0;??????????B:????dout=1b0;??????????C:????dout=1b0;?????????????D:????dout=1b0;??????????E:????dout=1b1;?????????default:dout=1b0;????????endcase??????end??endmodule更简洁的三段式always @ ( CS or din ) begin??NS = 5bx;??case (CS)????IDLE : NS = din ? A : IDLE;???????????A : NS = din ? A : B;???????????B : NS = din ? A : C;??????????C : NS = din ? D : IDLE;??????????D : NS = din ? A : E;??????????E : NS = din ? A : C;??????default: NS = IDLE;??????endcase?endalways @ ( posedge clk or negedge rst)???if (!rst)?