SignalTap II的使用.ppt

Quartus II Software Design Series : Verification Debugging Tools – SignalTap II Embedded Logic Analyzer SignalTap II ELA Agenda SignalTap II overview features Using SignalTap II interface Additional SignalTap II features When to Use SignalTap II ELA No external equipment available Design targets FPGA Additional device resources available for analyzer Faster data acquisition speeds JTAG connection available Performing functional debug SignalTap II ELA Captures the logic state of FPGA internal signals using a defined clock signal Gives designers ability to monitor buried signals Connects to Quartus II software through FPGA JTAG pins Captures real-time data Up to 270 MHz Is available for free Installed with full subscription or web edition Installed with stand-alone programmer How Does It Work? ELA Resource Utilization ELA uses device resources for implementation ALMs/LEs for ELA megafunction routing Memory for sample storage LE count is a function of the number of channels trigger levels Memory block count is a function of number of channels sample depth Selectable trade-off between depth number of channels 128K sample depth with 1024 channels not practical – 32,768 M4K blocks Feature Overview SignalTap II Agenda SignalTap II overview features Using SignalTap II interface Additional SignalTap II features SignalTap II Design Flow Use SignalTap II file (.STP) Use Quartus II GUI Configure STP details manually STP separate from design files Connect ELA to signals in any level of hierarchy Use MegaWizard? Plug-In Manager Instantiate directly into HDL ELA tied directly to signals in RTL See Appendix for more details Using STP File Create .STP file Assign sample clock Specify sample depth Assign signals to STP file Specify triggering Setup JTAG Save .STP file compile with design Program device Acquire data 1) Creating A New .STP File To create a .STP file Method 1 Tools menu ? SignalTap II Embedded Logic Analyzer Method 2 Select new (file menu) Other files S