11~12EDA期末试卷A答案.doc
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1、 entity 、 nor2 、 y=not(a or b)
2、 q:out std_logic 、 clkevent and clk=1 、 end if
第一处: y:out std_logic 改为y:out std_logic_vector(7 downto 0)
第二处: architecture bhv is 改为architecture bhv of dc38 is
第三处: case a is 改为case indate is
第四处: 在end case; 后加 end process; 寄存器传输级
SOPC 可编程片上系统
EAB 嵌入式阵列块
编程
1.
Architecture one of mymux is
Begin
Process (sel, ain, bin)
Begin
If sel = “00” then cout = ain or bin;
Elsif sel = “01” then cout = ain xor bin;
Elsif sel = “10” then cout = ain and bin;
Else cout = ain nor bin;
End if;
End process;
End one; Architecture two of mymux is
Begin
Process (sel, ain, bin)
Begin
Case sel is
when “00” = cout = ain or bin;
when “01” = cout = ain xor bin;
when “10” = cout = ain and bin;
when others = cout = ain nor bin;
End case;
End process;
End two; Architecture three of mymux is
Begin
Cout = ain or bin when sel = “00” else
Ain xor bin when sel = “01” else
Ain and bin when sel = “10” else ain nor bin;
End three; 2
该状态机为moore型状态机,输出数据outa和输入ina没有直接逻辑关系,outa是时钟clk的同步时序逻辑。 5
Library ieee;
Use ieee.std_logic_1164.all; 2
Entity mooreb is
Port (clk, reset : in std_logic;
Ina : in std_logic_vector (1 downto 0);
Outa : out std_logic_vector (3 downto 0) ); 3
End mooreb;
Architecture one of mooreb is
Type ms_state is (st0, st1, st2, st3);
Signal c_st, n_st : ms_state; 3
Begin
Process (clk, reset) 4
Begin
If reset = ‘1’ then c_st = st0;
Elsif clk’event and clk = ‘1’ then c_st = n_st;
End if;
End process;
Process (c_st) 8
Begin
Case c_st is
When st0 = if ina = “00” then n_st = st0;
Else n_st = st1;
End if;
Outa =
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