拉扎维《模拟集成电路设计》第二版课件 Ch2.ppt

* NMOS versus PMOS Devices PMOS devices are quite inferior to NMOS in most CMOS technology. Lower mobility of holes (μpCox ≈ 0.5μnCox) yield lower current drive and conductance. NMOS exhibit higher output resistance, providing more ideal current sources and higher gain in amplifiers. As such is it preferred to incorporate NMOS rather than PMOS wherever possible. * FinFETs FinFETs have three-dimensional geometry and exhibit superior performance as channel lengths fall below ~20 nm. Here, W = WF + 2HF, but since HF is not under the circuit designer’s control and WF, impacts device imperfections, there are only discrete values for transistor width. * FinFETs Spacing between fins, SF, also plays a significant role in performance and is typically fixed. Due to small dimensions of the intrinsic FinFET, the gate and S/D contacts must be placed away from the core of the device. * Behavior of MOS Devices as a Capacitor Recall that if source, drain, and bulk are grounded and the gate voltage rises, an inversion layer begins to form for VGS ≈ VTH, and the device operates in the subthreshold region for 0VGSVTH. The transistor can be considered a two-terminal device and we can examine its capacitance for different gate voltages. * Behavior of MOS Devices as a Capacitor A very negative VGS causes holes to be attracted in the substrate to the oxide interface, and say the MOSFET operates in the “accumulation region” with unit area capacitance of Cox. As VGS rises, the density of holes at the interface falls, a depletion region begins to form under the oxide, and the device enters weak inversion, causing capacitance to consist of a series combination of Cox and Cdep. As VGS exceeds VTH, the oxide-silicon interface sustains a channel and the unit area capacitance returns to Cox. * MOS Transconductance To find the transconductance for the topology on the left with respect to VDS, - So long as VDS ≥ Vb ? VTH, M1 is in saturation, so ID is relatively constant,