双语课件（第2章） 2. Logic gates 《数字设计基础（双语教学版）》Barry Wilknson 教学课件.ppt

2.6 Gates design Supply voltage The supply voltage for TTL is +5V. A logic 0 is represented by a voltage of +0.2V nominally, it can be generated between 0V and +0.4V. We often associate 0V with a logic 0. A logic 1 is represented by a voltage of +3.4V nominally, it can be generated between +2.4V and +5V. We often associate +5V with a logic 1. 2.6 Gates design Voltages as low as +2V will be recognized as logic 1. TTL voltages Voltages as high as +0.8V will be recognized as logic 0. 2.6 Gates design Noise Noise is the unwanted electrical signals occurring on wires in a system. Logic devices must be designed to accept a certain amount of electrical noise in the system and continue to operate correctly. Noise margin Noise margin is the level of voltage present as electrical noise that can be tolerated in the system. 2.6 Gates design Noise margin is given in terms of the allowable noise voltage that can be added to or subtracted from a generated logic signal with the logic signal still recognized at the input of gate as the logic level. In TTL, the noise margins at both a logic 0 and a logic 1 is +0.4V. 2.6 Gates design 2. Metal oxide silicon gates MOS transistor switches The MOS transistor has three terminals: the source terminal, the drain terminal, and the gate terminal. In a MOS transistor, to change the state of the transistor, a different voltage is applied to the gate terminal of the transistor. 2.6 Gates design When the transistor is switched off, no electrical conduction occurs between the source and the drain terminal. The voltage on the gate to control the on and off states is defined as the voltage across the gate and source terminals, Vgs. When the transistor is switched on, the electrical conduction occurs between the source and the drain terminal. 2.6 Gates design PMOS AND NMOS transistor There are two types of MOS transistor: the n-type MOS transistor (NMOS) and the p-type MOS transistor (PMOS). The n-type MOS transistor require