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XC9500XL High-Performance CPLD Family Data Sheet高性能CPLD系列产品介绍.pdf

发布:2019-11-28约7.54万字共18页下载文档
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k 0 R XC9500XL High-Performance CPLD Family Data Sheet DS054 (v2.2) July 25, 2006 0 0 Product Specification Features - Local clock inversion with three global and one product-term clocks • Optimized for high-performance 3.3V systems - Individual output enable per output pin with local - 5 ns pin-to-pin logic delays, with internal system inversion frequency up to 208 MHz - Input hysteresis on all user and boundary-scan pin - Small footprint packages including VQFPs, TQFPs inputs and CSPs (Chip Scale Package) - Bus-hold circuitry on all user pin inputs - Pb-free available for all packages - Supports hot-plugging capability - Lower power operation - Full IEEE Standard 1149.1 boundary-scan (JTAG) - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V support on all devices signals
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