Introduction_to_AMBA_AXI_3.0.pdf

Introduction to AMBA 3.0 AXI Chih-Tsun Huang (黃稚存) Department of Computer Science National Tsing Hua University Original Lecture from Prof. Juinn-Dar Huang, NCTU Outlines AXI overview Signal definitions Ch l h d h kianne an s a ng Addressing options Slave responses Protocol Details Transaction ordering Data transfers Clock and reset Fall 2008 CS4161 1Chih-Tsun Huang Background AXI (Advanced eXtensible Interface) by ARM Also known as AMBA 3.0 Debut in Embedded Processor Forum (EPF), 2003 Version 1.0 announced in March 2004 Fall 2008 CS4161 2Chih-Tsun Huang Objectives Provide high bandwidth and low latency Enable high frequency operations Fit for devices with high initial latency e.g., DRAM controllers Provide flexibility of interconnect architectures B (f ti ll ) b k d tibl ithe unc ona y ac war -compa e w existing AHB and APB not plug-n-play bus bridges are required Fall 2008 CS4161 3Chih-Tsun Huang Key Features Separate address/control and data phases Separate read and write channels to enable more efficient DMA controllers Burst-based transactions with only start address issued Unaligned data transfers using separate byte-lane strobes Multiple outstanding transactions Out of order transaction completion- - Latency-insensitive protocol by register slicing Fall 2008 CS4161 4Chih-Tsun Huang Channel Architecture Write Address/Control AWREADY Read Address/Control AXI AXI Write Data ARREADY Master SlaveWREADY Read Data RREADY Write Response BREADY Fall 2008 CS4161 5 5 unidirectional channels Chih-Tsun Huang Read Transaction (1/2) Read Address/Control ARREADY AXI Master AXI Slave Read Data RREADY Master issues address and control Fall 2008 CS4161 6 Chih-Tsun Huang Read Transaction (2/2) Read Address/Control ARREADY AXI Master AXI Slave Read Data RREADY Slave returns data and response Fall 2008 CS4161 7 Chih-Tsun Huang Write Transaction (1/3) Write Address/Control AWREADY Write Data AXI Master AXI Slave WREADY Write Response BREADY