Introduction_to_ASIC_verification.pdf

?2011, Meeta Yadav 1 ASIC Verification Course Overview Fall 2011 Meeta Yadav ?2011, Meeta Yadav 2 Course Overview This course covers the verification process used in validating the functional correctness in todays complex Application Specific Integrated Circuits (ASICs). Topics include fundamentals of simulation based functional verification, stimulus generation, results checking, coverage, debug, and assertions. Provides the students with real world verification problems to allow them to apply what they learn. Instructor Dr. Meeta Yadav Email: myadav@ Office hours: 4:00 to 5:00 Fridays, 3:00 to 4:00 Thursday (DE) TAS TBD Prerequisite ECE 520 ASIC Design or equivalent. A good working knowledge of Verilog or VHDL is essential. This is not suitable as a first course in a hardware description language. ?2011, Meeta Yadav 3 What is ASIC Verification? ?2011, Meeta Yadav 4 Design Complexity Increasing Image Processing Location-Based Services Telematics Broadcasting Computing Communication Entertainment Designs are becoming more complex as more functionality is added to them ?2011, Meeta Yadav 5 Increase in Transistors Per Die Increased functionality increases the number of transistors in the design thus increasing the possibility of error in the design ?2011, Meeta Yadav 6 6 [Collet 2005] Increase in Design Bugs 50% of ASICs require more than one respin 75% of them have logical or functional bugs ?2011, Meeta Yadav 7 7 Solution is: ASIC Verification Functional Verification Formal Verification ?2011, Meeta Yadav 8 ASIC Verification is: 1. Making sure there are no bugs in the design 2. All design functionality has been implemented ?2011, Meeta Yadav 9 What will you learn in this class? To develop a Verification Plan What to Verify? How to Verify it? Develop a reusable testbench Write Assertions Perform Coverage OOP VMM Methodology Think Get close to the bug When am I done? Close the gap ?2011, Meeta Yadav 10 ? Testbench functionality ? Generate stimulus ? App