Verilog HDL简明教程.pdf

Verilog HDL Verilog HDL Verilog HDL Verilog HDL Verilog HDL Verilog HDL Verilog C Verilog HDL Verilog HDL , Verilog HDL1 Verilog HDL2 HDL Verilog HDL3 Verilog Verilog HDL4 Verilog HDL5 - 1 - Verilog HDL 1 - 2 - Verilog HDL - 3 - Verilog HDL 2 HDL HDL 2.1 Verilog ; ; module module_name (port_list); Declarations: reg, wire, parameter, input, output, inout, function, task, . . . Statements: Initial statement Always statement Module instantiation Gate instantiation UDP instantiation Continuous assignment endmodule , module HalfAdder (A, B, Sum, Carry); input A, B; output Sum, Carry; assign #2 Sum = A ^ B; assign #5 Carry = A B; endmodule - 4 - Verilog HDL HalfAdder4 : A B Sum Carry, 1 , ,