《Cortex-M3 Training(chinese)》.ppt

Cortex-M3 Training Cortex-M3 Core Presentation CONTENTS 认识 Cortex-M3内核 架构 性能 与ARM7比较 Bit Banding Integrated Debug Capabilities Interrupt and real time capabilities Power management Benefits Cortex-M3 Processor 分层的处理集成内核和先进的系统外设 Cortex-M3 core 哈佛架构 3级流水线，分支预测 Thumb?-2 and traditional Thumb 累加器，硬件除，单周期乘 Cortex-M3 Processor Cortex-M3 core 可配置的中断控制器 Bus matrix Advanced debug components Optional MPU ETM (Not available in STM32F10x) Cortex-M3 Processor Overview (1/2) Cortex-M3 Processor Overview (2/2) 3级流水线 预取, 译码 执行 单周期乘 Cortex-M3 ARM7: Key Features Comparison Cortex-M3内核的附加特性 支持 只需2- or 3-pins 的调试方式 硬件中断处理使得中断完全摆脱汇编语言 Integrated atomic bit manipulation for improved data storage Extended Data Watchpoints Flash Patch technology Embedded sleep control and power-down modes 优化的 Memory Protection Unit (MPU) Embedded Trace Macrocell (ETM) High Performance CPU and Buses Bit Banding Debug Capabilities Privilege, Modes and Stacks 特权/非特权操作 Same as ARM7 Supervisor/User Thread 模式and Handler 模式 Handler mode is an exception or interrupt Thread mode is just normal application code running Main stack – Process stack 异常在特权模式下使用main stack Applications (thread mode) can use process stack 简化的寄存器集 Very simple, linear 4GByte address space No data pages No code pages Very compiler friendly Flexible register scheme Single-cycle multiply possible between any of the registers Any register can be used as a pointer to data structures/arrays Same “visible” register file as any other ARM architecture device Allowing unified assembler to mimic equivalent ARM instructions in Thumb-2 mode xPSR – Program Status Register Allows access to APSR, EPSR and IPSR special purpose registers PSR stored on stack during exceptions Condition code flags N = ALU的负标志位 Z = ALU的零标志位 C = ALU Operation carried out V = ALU操作溢出 Q = Saturated math overflow IT/ICI Bits Contain IF-THEN base condition code and Interrupt Continue information ISR Number ISR contains information on which exception was pre-empted