任意波形信号发生器源代码.doc

LIBRARY IEEE; --正弦信号发生器源文件 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY my; USE my.my_rom.ALL; ENTITY SINGT IS PORT ( CLK : IN STD_LOGIC; --信号源时钟 DOUT : OUT STD_LOGIC_VECTOR ((rom_width-1) DOWNTO 0) );--8位波形数据输出 END; ARCHITECTURE behav OF SINGT IS SIGNAL i:integer range 0 to (adr_high-1):=0;--设定内部节点作为地址计数器 BEGIN PROCESS(CLK) BEGIN if CLKevent and CLK=1 then if i = (adr_high-1) THEN i = 0; ELSE i = i + 1; END IF; end if; dout = my_rom(i); END PROCESS; END behav; LIBRARY IEEE; --正弦信号发生器源文件 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; PACKAGE my_rom IS CONSTANT rom_width : POSITIVE := 8; CONSTANT adr_high : POSITIVE := 64; SUBTYPE rom_word IS STD_LOGIC_VECTOR((rom_width-1) DOWNTO 0); TYPE rom_table IS ARRAY(0 TO (adr_high-1)) OF rom_word; CONSTANT my_rom:rom_table:= (11111110111110011110111111100001, --00-0f 11001111101110101010001010001001, -- 01110000010101110100000000101011, --10-1f 00011010000011010000010000000000, --00000001000010000001001100100010, --20-2f00110101010010110110001101111100, --10010110101011101100010111011001, --30-3f 11101001111101011111110011111111 );-- END;