OFDM基带处理器芯片设计与FPGA实现时间同步模块的部分代码.docx
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时间同步模块的部分代码
module Time_Syncronization(Clk,Rst_n,DataInEnable,DataInRe,DataInIm,DataOutEnable,DataOutRe,DataOutIm,DataSymbol);
input Clk;
input Rst_n;
input DataInEnable;
input [7:0]DataInRe;
input [7:0]DataInIm;
output DataOutEnable;
output [7:0]DataOutRe;
output [7:0]DataOutIm;
output [7:0]DataSymbol;
wire QuantizationEnable;
wire [15:0]Quantization_Result_Real;
wire [15:0]Quantization_Result_Imag;
Quantization Quantization (
.Clk(Clk),
.Rst_n(Rst_n),
.inEn(DataInEnable),
.bitInR(DataInRe),
.bitInI(DataInIm),
.QuantizationEnable(QuantizationEnable),
.Quantization_Result_Real(Quantization_Result_Real),
.Quantization_Result_Imag(Quantization_Result_Imag)
);
wire PeakFinded;
Match_Filtering MatchFiltering (
.Clk(Clk),
.Rst_n(Rst_n),
.QuanEnable(QuantizationEnable),
.QuanDataRe(Quantization_Result_Real),
.QuanDataIm(Quantization_Result_Imag),
.PeakFinded(PeakFinded)
);
Symbol_Output SymbolOutput (
.Clk(Clk),
.Rst_n(Rst_n),
.PeakFinded(PeakFinded),
.DataInRe(DataInRe),
.DataInIm(DataInIm),
.DataOutEnable(DataOutEnable),
.DataOutRe(DataOutRe),
.DataOutIm(DataOutIm),
.DataSymbol(DataSymbol)
);
endmodule
Part1: Quantization
module Quantization(Clk,Rst_n,inEn,bitInR,bitInI,QuantizationEnable,Quantization_Result_Real,Quantization_Result_Imag);
input Clk;
input Rst_n;
input inEn;
input [7:0]bitInR;
input [7:0]bitInI;
output QuantizationEnable;
reg QuantizationEnable;
output [15:0]Quantization_Result_Real;
output [15:0]Quantization_Result_Imag;
reg [15:0]Quantization_Result_Real;
reg [15:0]Quantization_Result_Imag;
reg BufferEnable;
reg [7:0]BufferDataR;
reg [7:0]BufferDataI;
always @(posedge Clk or negedge Rst_n)
begin
if(!Rst_n)
begin
BufferEnable = 0;
BufferDataR = 0;
BufferDataI = 0;
end
else
begin
if(inEn)
begin
BufferEnable = 1;
BufferDataR = bitInR;
BufferDataI = bitInI;
end
else
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