EDA实验报告实验三:序列信号发生器与检测器设计.docx
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实验三序列信号发生器与检测器设计一、实验目的1.学习一般有限状态机的设计;2.实现串行序列的设计。二、设计要求先设计0111010011011010序列信号发生器;再设计一个序列信号检测器,若系统检测到串行序列11010则输出为“1”,否则输出为“0”,并对其进行仿真和硬件测试。三、实验设备PC机,Quartueⅱ软件,实验箱四、实验原理1、序列信号发生器CNT00000001001000110100010101100111ZOUNT10001001101010111100110111101111ZOU位信号CLRN。当CLRN=0时,使CNT=0000,当CLRN=1时,不影响程序运行,每来一个CLK脉冲CNT加一。2、序列信号检测器状态转移图:五、实验步骤1、信号发生器建立工作库文件夹,输入设计项目VHDL代码,如下:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY XLSIGNAL16_1 IS PORT( CLK,CLRN:IN STD_LOGIC; ZOUT:OUT STD_LOGIC); END XLSIGNAL16_1;ARCHITECTURE one OF XLSIGNAL16_1 IS SIGNAL CNT:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ZREG:STD_LOGIC;BEGIN PROCESS(CLK,CLRN) BEGIN IF(CLRN=0)THEN CNT=0000;ELSE IF(CLKEVENT AND CLK=1)THEN CNT=CNT+1; END IF; END IF;END PROCESS;PROCESS(CNT) BEGIN CASE CNT IS WHEN0000=ZREG=0; WHEN0001=ZREG=1; WHEN0010=ZREG=1; WHEN0011=ZREG=1; WHEN0100=ZREG=0; WHEN0101=ZREG=1; WHEN0110=ZREG=0; WHEN0111=ZREG=0; WHEN1000=ZREG=1; WHEN1001=ZREG=1; WHEN1010=ZREG=0; WHEN1011=ZREG=1; WHEN1100=ZREG=1; WHEN1101=ZREG=0; WHEN1110=ZREG=1; WHEN1111=ZREG=0; WHEN OTHERS=ZREG=0; END CASE; END PROCESS; ZOUT=ZREG;END one;2)对其进行波形仿真,如下图:3)将其转换成可调用元件如图:2、信号检测器1)建立工作库文件夹,输入设计项目VHDL代码,如下:LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SCHK IS? PORT(DIN, CLK, CLR? : IN STD_LOGIC; ??????? ss : OUT STD_LOGIC_VECTOR END SCHK;ARCHITECTURE behav OF SCHK IS??? SIGNAL Q : INTEGER RANGE 0 TO 5 ;??? SIGNAL D : STD_LOGIC_VECTOR(5 DOWNTO 0);??? BEGIN??? D = 11010? ; ? PROCESS( CLK, CLR )? BEGIN? IF CLR = 1 THEN??? Q = 0 ;? ELSIF? CLKEVENT AND CLK=1 THEN??CASE Q IS? WHEN 0=? IF DIN = D(4) THEN Q = 1 ; ELSE Q = 0 ; END IF ;? WHEN 1=? IF DIN = D(3) THEN Q = 2 ; ELSE Q = 0 ; END IF ;? WHEN 2=? IF DIN = D(2) THEN Q = 3 ; ELSE Q = 2 ; END IF ;? WHEN 3=? IF DIN = D(1) THEN Q = 4 ; ELSE Q = 0 ; END IF
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