现代计算机组成原理——除法器设计.doc

数字系统组成原理和设计技术 实验：除法器 学号 1115108052 姓名 詹炳鑫 班级 电子2班 华侨大学电子工程系 程序 LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY devide IS PORT ( reset, clock, start : IN STD_LOGIC; x : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); y : IN STD_LOGIC_VECTOR( 8 DOWNTO 0 ); done, overflow : OUT STD_LOGIC; q, r : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ) ); END devide; ARCHITECTURE behav OF devide IS SIGNAL rx : STD_LOGIC_VECTOR( 5 DOWNTO 0 ); SIGNAL ry : STD_LOGIC_VECTOR( 5 DOWNTO 0 ); SIGNAL rq : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); SIGNAL rmd : STD_LOGIC_VECTOR( 5 DOWNTO 0 ); SIGNAL flag_subadd : bit; SIGNAL state : integer RANGE 0 TO 6; BEGIN PROCESS ( reset, clock ) VARIABLE sq : STD_LOGIC; BEGIN IF reset = 0 THEN rx = ( OTHERS = 0 ); ry = ( OTHERS = 0 ); rq = ( OTHERS = 0 ); state = 0; ELSIF clockevent AND clock = 1 THEN CASE STATE IS WHEN 0 = rx( 5 DOWNTO 0 ) = x(4) x( 4 DOWNTO 0 ) ; ry( 5 DOWNTO 0 ) = y(8) y( 8 DOWNTO 4 ) ; rq( 4 DOWNTO 0 ) = y( 3 DOWNTO 0 ) 0; flag_subadd = 1; done = 0; overflow = 0; IF start = 1 THEN state = 1; END IF; WHEN 1 = IF rmd(5) = 0 THEN overflow = 1; state = 0; done = 1; ELSE state = state + 1; sq := 0; ry( 5 DOWNTO 0 ) = rmd( 4 DOWNTO 0 ) rq(4); rq( 4 DOWNTO 0 ) = rq( 3 DOWNTO 0 ) sq; flag_subadd = 0; END IF; WHEN 5 = IF rmd(5) = 0 THEN sq := 1; flag_subadd = 1; ELSE sq := 0; flag_subadd = 0; END IF; ry( 5 DOWNTO 0 ) = rmd( 4 DOWNTO 0 ) rq(4); ry( 5 DOWNTO 0 ) = rmd( 5 DOWNTO 0 ); rq( 4 DOWNTO 0 ) = rq( 3 DOWNTO 0 ) sq; state = state + 1; WHEN 6 = IF rq(0) = 0 THEN ry = rmd( 5 DOWNTO 0 ); r = rmd( 4 DOWNTO 0 ); ELSE r = ry( 4 DOWNTO 0); END IF; state = 0; q = rq; done = 1 ; WHEN OTHERS = IF rmd(5) = 0 THEN sq := 1; flag_subadd = 1; ELSE sq := 0; flag_subadd = 0; END IF; ry( 5 DOWNTO 0 ) = rmd( 4 DOWNTO 0 ) rq(4); rq( 4 DOWNTO 0 ) = rq( 3 DOWNTO 0 ) sq; state = state + 1; END CASE; END IF; END PROCESS; rmd = ry + rx WHEN flag_subadd = 0 ELSE ry + NOT rx + 1; END