第5章VHDL设计初步new.ppt
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第五章;一、什么是VHDL？;二、VHDL的功能和标准？;Altera VHDL ;;四、VHDL 设计流程 ： V-S-F-P; A、用VHDL设计一个2选1多路通道;A、设计一个2选1多路通道; VHDL基本语法小结 1;B、用VHDL设计一个D触发器;比较用4种不同语句的D触发器VHDL程序; VHDL基本语法小结 2;C、用VHDL设计4位加法器;加数;8位被加数; VHDL基本语法小结 3;D、用VHDL设计4位计数器; ? 定输出信号数据类型为整数类型：
INTEGER，必须定义整数取值范围， RANGE 15 DOWNTO 0;4位锁存器; 4位计数器设计小结;E、用VHDL设计7段16进制译码器;;4位二进制减计数器：?
LIBRARY?IEEE;?
USE?IEEE.STD_LOGIC_1164.ALL;?
USE?IEEE.STD_LOGIC_UNSIGNED.ALL;??
ENTITY?MIN?IS????
PORT(clk,reset:IN?STD_LOGIC;???????
??q:OUT?STD_LOGIC_VECTOR(3?DOWNTO?0));?
END?MIN;??
ARCHITECTURE?struc?OF?MIN?IS???
SIGNAL?q_temp:STD_LOGIC_VECTOR(3?DOWNTO?0);?
BEGIN???
PROCESS(clk)???
BEGIN????
?IF(clkEVENT?AND?clk=1)THEN???????
IF?reset=0THEN?????????
?q_temp=1111;??????
?ELSIF?q_temp=0000?THEN??????????
q_temp=1111;???????
ELSE??????????
q_temp=q_temp-1;???????????
END?IF;?????
END?IF;??
?END?PROCESS;???
q=q_temp;?
END?struc;?
从状态‘1111’到状态‘0000’，然后再跳回‘1111’。异步复位不需要跟随脉冲变化，要立即复位。?;8421码十进制计数器：?
LIBRARY?IEEE;?
USE?IEEE.STD_LOGIC_1164.ALL;?
USE?IEEE.STD_LOGIC_UNSIGNED.ALL;??
ENTITY?TEN?IS???
PORT(clk,reset:IN?STD_LOGIC;????????
q:OUT?STD_LOGIC_VECTOR(3?DOWNTO?0));?
END?TEN;??
ARCHITECTURE?struc?OF?TEN?IS???SIGNAL?q_temp:STD_LOGIC_VECTOR(3?DOWNTO?0);?
BEGIN???PROCESS(clk)?
BEGIN
IF(clkEVENT AND clk=1)THEN
IF reset=1THEN
q_temp=0000;
ELSIF q_temp=1001THEN
q_temp=0000;
ELSE
q_temp=q_temp+1;
END IF;
END IF;
END PROCESS;
q=q_temp;
END struc;
从状态‘0000’到状态‘1001’，然后再跳回‘0000’，异步复位要立即复位。; VHDL基本语法小结 5;/wiki/VHDL;D-type flip-flops;library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; -- for the unsigned type
entity COUNTER is
generic ( WIDTH : in natural := 32);
port ( RST : in std_logic;
CLK : in std_logic;
LOAD : in std_logic;
DATA : in std_logic_vector(WIDTH-1 downto 0);
Q : out std_logic_vector(WIDTH-1 downto 0));
end entity COUNTER;
architecture RTL of COUNTER is
signal CNT : unsigned(WIDTH-1 downto 0);
begin process(RST, CLK) is
begin if RST = 1
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