第3章_VHDL设计初步.ppt

EDA 技术实用教程 第 3 章 VHDL设计初步 3.1 组合电路的VHDL描述 3.1.5 1位二进制全加器的VHDL描述 习 题 习 题 3-2 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41 IS PORT ( s0, s1 : in std_logic; a,b,c,d: in std_logic; y: out std_logic); END ENTITY mux41; ARCHITECTURE behave1 OF mux41 IS SIGNAL s :std_logic_vector(1 downto 0); BEGIN S= s1 s0; y=a WHEN s=00 ELSE b WHEN s=01 ELSE c WHEN s=10 ELSE d WHEN s=11 ELSE 0; END behave1; 多选择控制的IF语句 IF 条件1 THEN 顺序语句 l ; ELSIF 条件2 THEN 顺序语句2; ….. ELSIF 条件n THEN 顺序语句n; ELSE 顺序语句n+1; END IF; … ARCHITECTURE behave2 OF mux41 IS SIGNAL s :std_logic_vector(1 downto 0); BEGIN s = s1 s0; PROCESS (s,a,b,c,d) BEGIN IF s=00 THEN y=a ; ELSIF s=01 THEN y=b ; ELSIF s=10 THEN y=c ; ELSE y=d; END IF; END PROCESS; END behave2; … ARCHITECTURE behave3 OF mux41 IS SIGNAL s :std_logic_vector(1 downto 0); BEGIN s = s1 s0; PROCESS (s,a,b,c,d) BEGIN CASE s IS WHEN 00= y=a; WHEN 01= y=b; WHEN 10= y=c; WHEN 11= y=d; WHEN OTHERS = y=0; END CASE; END PROCESS; END behave3; 习 题 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY muxk IS PORT ( a1,a2,a3:in std_logic; s0,s1: in std_logic; outy: out std_logic); END ENTITY muxk; ARCHITECTURE behave OF muxk IS SIGNAL tmp :std_logic; SIGNAL outx :std_logic; BEGIN Pr1:PROCESS (a2,a3,s0) BEGIN CASE s0 IS WHEN 0= tmp=a2; WHEN 1= tmp=a3; WHEN OTHERS = tmp=0; END CASE; END PROCESS; Pr2:PROCESS (a1,tmp,s1) BEGIN CASE s1 IS WHEN 0= outx=a1; WHEN 1= outx=tmp; WHEN OTHERS = outx=0; END CASE; END PROCESS; outy=outx; END behave; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21a IS PORT ( a,b:in std_logic; s: in std_logic; y: out std_logic); END ENTITY mux21a; ARCHITECTURE behave OF mux21a IS BEGIN y=a WHEN s=0 ELSE b