实验位十进制计数器的设计.doc

实验二 4位十进制计数器的设计 一、实验目的： 1、深入理解信号和变量的区别 2、深入理解并行语句和语句的区别； 3深入理解异步和同步的概念； 4掌握的设计方法； 5能会看最大系统运行频率和资源使用报告。 四位十进制计数器程序A： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bcd_counter is port ( clk : in std_logic; reset : in std_logic; co : out std_logic; q : out std_logic_vector(3 downto 0) ); end entity; architecture bev of bcd_counter is begin process (clk) variable cnt : std_logic_vector(3 downto 0); begin if (rising_edge(clk)) then if reset = 1 then cnt := 0000; else if cnt 9 then cnt := cnt + 0001; else cnt := 0000; co = 1; end if; end if; end if; q = cnt; end process; end bev; 四位十进制计数器程序B： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bcd_counter2 is port ( clk : in std_logic; reset : in std_logic; co : out std_logic; q : out std_logic_vector(3 downto 0) ); end entity; architecture bev of bcd_counter2 is signal cnt : std_logic_vector(3 downto 0); begin process (clk) begin if (rising_edge(clk)) then if reset = 1 then cnt = 0000; else if cnt 9 then cnt = cnt + 0001; else cnt = 0000; co = 1; end if; end if; end if; end process; q = cnt; end bev; 四位十进制计数器程序C： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bcd_counter3 is port ( clk : in std_logic; reset : in std_logic; co : out std_logic; q : out std_logic_vector(3 downto 0) ); end entity; architecture bev of bcd_counter3 is signal cnt : std_logic_vector(3 downto 0); begin process (clk) begin if reset = 1then cnt = 0000; elsif (rising_edge(clk)) then if cnt 9 then cnt = cnt + 0001; else cnt = 0000; co = 1; end if; end if; end process; q = cnt; end bev; 三、实验内容： 1、资源使用情况和最大运行频率 程序 使用逻辑单元数 寄存器数 运行频率） 1