fgpa程序（国外英文资料）.doc

fgpa程序（国外英文资料） The 15.2 parallel data stream is transformed into a design of a special serial data flow module Design of two modules: data can be integrated the first module (M1) can convert four parallel data to conform to the following agreement of serial data stream, data stream with SCL and sda two lines, The SCLK inputs the clock signal for the data, data [3:0] for the input data, and the ack signals the input for the data. The second module (M2) can receive and transform information from the serial data stream For the high level of 16 signal lines, if the data is 1, the first line is high level, the data is n, and the NTH line is high level. M0 is the test signal module. This module accepts M1 The ack signal generates new test data data [3:0]. Communication protocol: SCL is the continuous output of clock signals, if SCL is high level, sda is low by high, and serial data flow begins; If SCL is high level, sda is low, and the serial data ends The serial data bits of the sda signal must be changed in the SCL for low power, or zero if it becomes high. / /... The ptosda. V file begins... / / / *... The module (M1) function: the four parallel data types that are entered into the protocol requirements are converted by the design requirements, and the output is matched by SCL and sda ... This module is an RTL integrated module... * / Module TEST1 (SCLK, d_ena, SCL, sda, RST, data, ack); Input SCLK, RST; Input d_ena; Input [3:0] data; / / parallel port data input The output ack; / / request new conversion data The output SCL. Inout sda. / / define sda for one-way serial output, a two-way serial bus Reg SCL, link_sda, ack, sdabuf; Reg [3-0] databuf; Reg [3-0] state; The assign sda = link_sda? Sdabuf: 1 bz. / / link_sda controls sdabuf to the serial bus Parameter ready = 8 b0000_0000, Start = 8 b0000_0001, Bit1 = 8 b0000_0010, Bit2 = 8 b0000_0100, Bit3 = 8 b0000_1000, Bit4 = 8 b0001_0000, Bit5 = 8 b0010_0000, Stop = 8 b0100_0000, IDLE = 8 b1000_0000; The posedge SCLK or