ultra low-power algorithm design for implantable devices application to epilepsy prostheses超小功率算法设计为植入式设备应用癫痫假肢.pdf

J. Low Power Electron. Appl. 2011, 1, 175-203; doi:10.3390/jlpea1010175 OPEN ACCESS Journal of Low Power Electronics and Applications ISSN 2079-9268 /journal/jlpea Review Ultra Low-Power Algorithm Design for Implantable Devices: Application to Epilepsy Prostheses Shriram Raghunathan , Sumeet K. Gupta , Himanshu S. Markandeya , Pedro P. Irazoqui and Kaushik Roy Center for Implantable Devices, Weldon School of Biomedical Engineering, Purdue University, West Lafayette, IN 47907, USA; E-Mails: pip@ (P.P.I.); kaushik@ (K.R.) School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA; E-Mails: guptask@ (S.K.G.); hmarkand@ (H.S.M.) Author to whom correspondence should be addressed; E-Mail: sraghun@; Tel.: +1-765-714-1606. Received: 10 November 2010; in revised form: 11 April 2011 / Accepted: 14 April 2011 / Published: 12 May 2011 Abstract: Low-power circuit design techniques have enabled the possibility of integrating signal processing and feature extraction algorithms on-board implantable medical devices, eliminating the need for wireless transfer of data outside the patient. Feature extraction algorithms also serve as valuable tools for modern-day artificial prostheses, made possible by implantable brain-computer-interface systems. This paper intends to review the challenges in designing feature extraction blocks for impla