嵌入式系统原理与应用教学课件作者魏权利S3C2410寄存器地址C定义课件.doc

/* * vivi/include/s3c2400.h * * Definition of constants related to the S3C2410 microprocessor(based on ARM 290T). * This file is based on the S3C2400 User Manual 2002,01,23. * * Copyright (C) 2002 MIZI Research, Inc. * * Author: Janghoon Lyu nandy@ * Date : $Date: 2002/10/11 02:27:29 $ * * $Revision: 1.8 $ */ /* * History * * 2002-05-14: Janghoon Lyu nandy@ * - Initial code */ #include hardware.h #include bitfield.h #define USR26_MODE 0x00 #define FIQ26_MODE 0x01 #define IRQ26_MODE 0x02 #define SVC26_MODE 0x03 #define USR_MODE 0x10 #define FIQ_MODE 0x11 #define IRQ_MODE 0x12 #define SVC_MODE 0x13 #define ABT_MODE 0x17 #define UND_MODE 0x1b #define SYSTEM_MODE 0x1f #define MODE_MASK 0x1f #define F_BIT 0x40 #define I_BIT 0x80 #define CC_V_BIT (1 28) #define CC_C_BIT (1 29) #define CC_Z_BIT (1 30) #define CC_N_BIT (1 31) /* Memory Controller */ #define MEM_CTL_BASE 0#define bMEMCTL(Nb) __REGl(MEM_CTL_BASE + (Nb)) /* Offset */ #define oBWSCON 0x00 /* R/W, Bus width and wait status ctrl reg. */ #define oBANKCON0 0x04 /* R/W, Bank 0 control reg. */ #define oBANKCON1 0x08 /* R/W, Bank 1 control reg. */ #define oBANKCON2 0x0C /* R/W, Bank 2 control reg. */ #define oBANKCON3 0x10 /* R/W, Bank 3 control reg. */ #define oBANKCON4 0x14 /* R/W, Bank 4 control reg. */ #define oBANKCON5 0x18 /* R/W, Bank 5 control reg. */ #define oBANKCON6 0x1C /* R/W, Bank 6 control reg. */ #define oBANKCON7 0x20 /* R/W, Bank 7 control reg. */ #define oREFRESH 0x24 /* R/W, SDRAM refresh control register */ #define oBANKSIZE 0x28 /* R/W, Flexible bank size register */ #define oMRSRB6 0x2C /* R/W, Mode register set register bank 6 */ #define oMRSRB7 0x2C /* R/W, Mode register set register bank 7 */ /* Registers */ #define BWSCON bMEMCTL(oBWSCON) #define BANKCON0 bMEMCTL(oBANKCON0) #define BANKCON1 bMEMCTL(oBANKCON1) #define BANKCON2 bMEMCTL(oBANKCON2) #define BANKCON3 bMEMCTL(oBANKCON3) #define BANKCON4 bMEM