Analysis of a Memory Architecture for Fast （分析内存架构的快）.pdf

Analysis of a Memory Architecture for Fast Packet Buffers Sundar Iyer, Ramana Rao Kompella, Nick McKeown Computer Systems Laboratory, Stanford University, Ph: (650)-725 9077, Fax: (650)-725 6949 Stanford, CA 94305-9030 {sundaes, ramana, nickm}@stanford.edu Abstract -- All packet switches contain packet buffers to hold packets Second, interfaces with faster line rates require larger buffers. during times of congestion. The capacity of a high performance router is As a rule-of-thumb, packet switches employ buffers of size often dictated by the speed of its packet buffers. This is particularly true for approximately RTT × R (where RTT is the round trip time for a shared memory switch where the memory needs to operate at N times the line rate, where N is the number of ports in the system. Even input queued flows passing through the packet switch) for those occasions switches must be able to buffer packets at the rate at which they arrive. And when the packet switch is the bottleneck for the (TCP) flows so as link rates increase memory bandwidth requirements grow. With passing through it. With an Internet RTT of approximately 0.25 today’s DRAM technology and for an OC192c (10Gb/s) link, it is barely pos- seconds today, a 10Gb/s interface requires 2.5Gbits of memory. sible to write packets to (read packets from) memory at the rate at which