Best Practices for Implementing ARM Cortex （最佳实践实现手臂的皮层）.pdf

Best Practices for Implementing ARM ® TM Cortex -A12 Processor and Mali -T6XX GPUs for Mid-Range Mobile SoCs. Cortex-A12: ARM-Cadence collaboration Joint team working on ARM® Cortex® -A12 iRM flow iRM content: • Design constraints • Floorplan files • CPF files for low power flows. • Cadence flow scripts, e.g. RC EDI, based on Foundation flow scripts. • Makefile to run the whole flow. • iRM User Guide document Optimized Optimized EDA Flow Physical IP Experienced Cadence ARM support at EAC Evaluate EDA Tool Cortex-A12 Releases iRM Support RTL CPF 2 © 2012 Cadence Design Systems, Inc. All rights reserved. Cortex-A12 Cadence iRM Flow RTL Libraries CPF FP SDC Synthesis Physical Synthesis RTL Compiler Physical v12.2 ATPG netlist SDC CPF PLACEMENT Encounter Test v12.10 PR (gigaOpt, CCOPT, Nanoroute) Parasitics Extraction Encounter Digital Implementation v11.1 QRC v11.12 netlist SDC