数字系统设计与Verilog HDL-CPLD、FPGA基础知识.ppt

完全的低成本解决方案，新的低成本配置器件大大降低了整个解决方案的成本，大批量购买配置器件的定价只有$1~$3。 在Cyclone器件中可以实现一个低成本的CPU。 在一片EP1C3中，CPU和外围设备只占用器件资源不到1500个逻辑单元，成本低于$2。 Many customers like to see the floorplan for new devices to understand how they are laid out M4K (green), PLLs (grey) and logic elements (blue) are arranged in vertical columns Notice that unlike other device families, the PLLs are embedded into the logic array rather than on the periphery – this greatly reduced the die size of the part, making it entirely dependent on the size and number of I/O elements与其他器件系列不同，PLL是嵌入在逻辑阵列中，而不是位于外围，这样就大大减小了该部分的芯片尺寸，使芯片尺寸完全依赖于I/O单元的尺寸和数量。 参见《基于FPGA的嵌入式系统设计》P19 Cyclone器件的嵌入式存储器由1列或2列M4K存储器块组成。EP1C3、EP1C6有1列M4K块，EP1C12、EP1C20有2列M4K块。 The Cyclone embedded memory consists of columns of M4K memory blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while EP1C12 and EP1C20 devices have two columns Identical to Stratix M4K blocks, with the exception of performance 与Stratix M4K 块相同，只是性能不同 Very similar to APEX embedded system blocks (ESBs) except that there are more of them with enhanced functionality 与APEX的嵌入式系统块ESB非常相似，只是数量更多，以增强功能。 DDR ：Double Data Rate，双数据速率 SDRAM：Synchronous Dynamic RAM，同步动态随机存储器 FCRAM：Fast Circle RAM，快速循环RAM Double data rate SDRAM devices are expected to become the lowest cost memory solution in the next few years, even cheaper than single data rate SDRAM As such, many volume-driven, cost-sensitive applications are using DDR SDRAMs FCRAM devices provide faster performance at lower power and are based on the same fundamental architecture Dedicated interface circuitry is supported in Cyclone devices, in the top and bottom I/O banks The left and right I/O banks also support DDR SDRAM interfacing, but under certain conditions – please consult the datasheet for more details 64-Bit/66-MHz PCI is not supported in the EP1C3, EP1C6, and EP1C12 because of the significant number of I/O pins required SPI——Serial Peripheral Interface，串行外设接口； I2C——Inter-Integrated Circuit，内置集成电路。I2C总线是一种