寄存器实验.doc

并入串出移位寄存器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity piso is port(clk:in std_logic; clr:in std_logic; din:in std_logic_vector(7 downto 0); dout:out std_logic); end; architecture one of piso is signal cnt:std_logic_vector(2 downto 0); signal q:std_logic_vector(7 downto 0); begin process(clk) begin if clkevent and clk=1 then cnt=cnt+1; end if; end process; process(clk,clr) begin if clr=1 then q elsif clkevent and clk=1 then if cnt000 then q(7 downto 1)=q(6 downto 0); elsif cnt=000 then q=din; end if; end if; end process; dout=q(7); end; 串入串出移位寄存器 library ieee; use ieee.std_logic_1164.all; entity shift is port(clk:in std_logic; din:in std_logic; dout:out std_logic); end; architecture one of shift is signal q_temp:std_logic_vector(7 downto 0); begin process(clk) begin if clkevent and clk=1 then q_temp(0)=din; for i in 1 to 7 loop q_temp(i)=q_temp(i-1); end loop; end if; end process; dout=q_temp(7); end;