VHDL程序设计题讲课稿.docx
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VHDL 程 序 设 计 题
VHDL程序设计题
四、编程题(共50分)
1、请补全以下二选一 VHDL程序(本题10分)
En tity mux is
port(dO,d1,sel:in bit;
TOC \o 1-5 \h \z q:out BIT ); (2)
end mux;
architecture conn ect of MUX is (4)
sig nal tmpl, TMP2 ,tmp3:bit; (6)
begin
cale:
block
begin
tmp1=d0 and sel;
tmp2=d1 and (not sel)
tmp3= tmpl and tmp2;
TOC \o 1-5 \h \z q = tmp3; (8)
end block cale;
end CONNECT : (10)
2、编写一个2输入与门的VHDL程序，请写出库、程序包、实体、构造体相关语句，将 端口定义为标准逻辑型数据结构（本题 10分）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ( 2)
ENTITY nand2 IS
PORT (a，b:IN STD_LOGIC; (4)
y:OUT STD_LOGIC); (6)
END nan d2;
ARCHITECTURE nan d2_1 OF nand2 IS (8)
BEGIN
y = a NAND b;--与 y =NOT( a AND b);等价 (10) END nan d2_1;
3、根据下表填写完成一个 3-8线译码器的VHDL程序（16分）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY decoder_3_to_8 IS
(2)PORT (a,b,c,g1,g2a,g2b:IN STD_LOGIC;
(2)
y:OUT STD_L0GIC_VECT0R(7 DOWNTO 0)):
END decoder_3_to_8;
ARCHITECTURE rtl OF decoder_3_to_8 IS
SIGNAL in data:STD_LOGIC_VECTOR (2 DOWNTO 0);
(4)
BEGIN
in data = c b a;
(6)
PROCESS (in data,g1,g2a,g2b)
BEGIN
IF (g1 = 1 AND g2a = O AND g2b = O ) THEN
(8)
CASE in data IS
WHEN 000= y =
WHEN 001 = y =
WHEN 010 = y =
(10)
WHEN 011 = y =
WHEN 100 = y =
WHEN 101 = y =
WHEN 110 = y =
(12)
WHEN 111 = y =
WHEN OTHERS= y = XXXXXXXX;
END CASE;
ELSE
(14)y =(14)
END IF;
END PROCESS;
(16)
END rtl;
4、三态门电原理图如右图所示，真值表如左图所示，请完成其 VHDL程序构造体部分。
（本题14分）
控倒用扎数堀怖岀dinCHdoui
控倒用扎
数堀怖岀
din
CH
doui
X
0
2
0
0
1
1
1
表7-5三杰门奠值袤
图了-贮 2总门电閱
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tri_gate IS
P0RT(di n,e n:IN STD_LOGIC;
dout : OUT STD_LOGIC);
END tri_gate ;
ARCHITECTURE zas OF tri_gate IS
BEGIN
PROCESS (di n,e n)
BEGIN
IF (en= 1) THEN dout = din;
ELSE dout = Z;
END IF;
END PROCESS ;
END zas ;
四、编程题（共50分）
1、根据一下四选
程序的结构体部分，完成实体程序部分（本题
8分）
en tity MUX4 is
parti
(2)
s：
in std logic vector(1 downto 0);
(4)
d：
in std logic vector(3 downto 0);
⑹
y
out std logic
end MUX4;
architecture behave of MUX4 is begin
process(s)
be
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