基于CPU仿真器的汇编语言学习系统设计与实现_盛羽.pdf

第 41 卷第 6 期 中南大学学报( 自然科学版) Vol.41 No.6 2010 年 12 月 Journal of Central South University (Science and Technology) Dec. 2010 基于CPU 仿真器的汇编语言学习系统设计与实现 盛羽，余进，陈松乔，王建新 ( 中南大学 信息科学与工程学院，湖南 长沙，410083) 摘 要：提出一种基于 CPU 仿真器的汇编语言学习系统设计模型和实现方法。该系统利用 JavaBean 组件技术实 现 CPU 的仿真；结合多线程技术和锁机制实现组件的数据触发式调度机制，有效地解决了具有复杂关系的组件 之间的调度运行问题，保证了微命令的有序执行；基于脉冲信号的事件触发机制，实现了微指令的单步调试；基 于所设计的 CPU 仿真器指令系统，采用现代编译技术设计了一种汇编器，实现了 CPU 仿真器上汇编指令到机器 指令的快速编译。与已有的汇编语言学习系统相比，本系统不仅在通用性、交互性等方面都有较大提高，而且能 形象直观地展示虚拟寄存器等各个虚拟芯片的实时状态，记录对应的微指令流，从而更精确地监视汇编指令在 CPU 仿真器中的执行过程。 关键词：CPU 仿真器；汇编语言；编译技术；微指令流 中图分类号：TP391.9 文献标志码：A 文章编号：1672−7207(2010)06−2224−07 Design and implementation of assembly language learning system based on CPU simulator SHENG Yu, YU Jin, CHEN Song-qiao, WANG Jian-xin (School of Information Science and Engineering, Central South University, Changsha 410083, China) Abstract: An assembly language learning system (ASMLL), which is based on the CPU simulator, was presented. ASMLL simulated CPU with the JavaBean component technology. By using multi-thread technology and lock mechanism, ASMLL realized a scheduling mechanism based on component data triggered, which is an effective solution to deal with the scheduling problems of these components with complex relationship between each other, and can ensure micro-orders to run in an orderly implementation. Pulse signal based event triggered mechanism can implement the single-step debugging of enables microinstruction. Based on the instruction system of CPU simulator, a kind of assembler with modern c