Analytical Modeling and Reduction of Direct Tunneling Current during Behavioral Synthesis o.pdf

Analytical Modeling and Reduction of Direct Tunneling Current during Behavioral Synthesis of Nanometer CMOS Circuits Saraju P. Mohanty, Valmiki Mukherjee, and Ramakrishna Velagapudi Department of Computer Science and Engineering University of North Texas, Denton, TX 76203. Email : smohanty,vm0058,rv0063@ Abstract channel punch through current [2]. While biased diode leak- age and SiO tunnel current flow during both active and Gate oxide direct tunneling current is the major component sleep mode of the circuit, the other currents flow during the of static power dissipation of a CMOS circuit for low-end sleep mode only. technology, where the gate dielectric (SiO ) thickness is very Several methods have been proposed in literature for re- low. This paper presents a novel direct tunneling current re- ducing sleep mode leakage, such as use of multiple thresh- duction method during behavioral synthesis of nanometer old CMOS [3, 4], body-biasing [5], and state assignment [6]. CMOS circuits. We provide analytical models to calculate However, the leakage during active mode of a device has the direct tunneling current and the propagation delay of be- not got much attention, which is a prominent component of havioral level components. We then characterize those com- leakage for low-end nanotechnology [7]. As per ITRS high ponents for various gate oxide thicknesses. We also provide performance CMOS circuits will require gate oxide thick- an algorithm for behavioral scheduling for minimizing the ness of in near future