Datapath Scheduling using Dynamic Frequency Clocking.pdf

Datapath Scheduling using Dynamic Frequency Clocking Saraju P. Mohanty N. Ranganathan V. Krishna Department of Comp Sc and Engg Center for Microelectronics Research Agilent Technology University of South Florida University of South Florida Tampa, FL 33620 Tampa, FL 33620 Palo Alto, CA 94303 smohanty@ ranganat@ vamsi@ Abstract In this paper, we describe a new datapath scheduling al- gorithm called DFCS based on the concept of dynamic fre- quency clocking. In dynamic frequency clocking scheme, all functional units in the datapath are driven by a sin- gle clock line that switches frequency dynamically at run time. The algorithm schedules lower frequency operators at earlier steps and delays higher frequency operators to later steps. Next, it regroups some of the higher frequency operators with low frequency operators so as to meet the time constraint. During this phase, DFCS assignes the fre- quency for each cycle and the functional unit with the cor- responding voltage. The algorithm has been applied to var- ious high level synthesis benchmark circuits under different time constraints. The experimental results show that using three supply voltage levels 
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 ! # the critical path delay), av- erage energy savings in the range of $% to $% is obtained with respect to using a single-frequency and single-voltage scheme. 1 Introduction High-level synthesis is the transformation from a behav- ioral specification of a system to its RTL structure speci- fication [1]. The essential tasks involved in synthesis are scheduling, allocation, binding and clock selection. The need for low power synthesis is driven by several factors such as [6]: (1) demand of portable systems (battery life), (2) thermal considerations (cooling and packaging), (3) en- vironmental concerns (natural resources), and (4) reliability issues. The average power dissipation is a concern for the first three factors, whereas, p