哈工大计算机组成大作业.docx

计算机组成原理自主实验报告第四章‐实验1一个2114 存储芯片的实现要求：外特性与2114 芯片一致（P77，图4.12），可以设计成为64*64 个存储单元的堆。A0-A9：地址线I/O：数据输入输出线CS：片选信号R/W：读写信号VHDL代码：library IEEE;use IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity shiyan41 isPORT(clk, we, cs,reset: in STD_LOGIC;data: inout STD_LOGIC_VECTOR(3 downto 0);adr: in STD_LOGIC_VECTOR(9 downto 0));end shiyan41;architecture Behavioral of shiyan41 istype mem is array (63 downto 0) of STD_LOGIC_VECTOR(63 downto 0);signal data_in: STD_LOGIC_VECTOR(3 downto 0);signal data_out: STD_LOGIC_VECTOR(3 downto 0);signal sram : mem;signal cs_s : std_logic; signal we_s : std_logic;signal addr_in_row: std_logic_vector(5 downto 0);signal addr_in_col: std_logic_vector(3 downto 0);begincs_s = cs;we_s = we;addr_in_row = adr(8 downto 3);addr_in_col = adr(9) adr(2 downto 0);process(clk)beginif clkevent and clk=1 thenif(cs_s=0 and we_s=0) thensram(conv_integer(addr_in_row))(conv_integer(addr_in_col)) = data_in(0);sram(conv_integer(addr_in_row))(conv_integer(addr_in_col)+16) = data_in(1);sram(conv_integer(addr_in_row))(conv_integer(addr_in_col)+32) = data_in(2);sram(conv_integer(addr_in_row))(conv_integer(addr_in_col)+48) = data_in(3);end if;end if;end process;process(clk,reset)beginif reset = 1 thendata_out = (others = 0);elsif clkevent and clk=1 thenif cs=0 and we=1 thendata_out = sram(conv_integer(addr_in_row))(conv_integer(addr_in_col)+48) sram(conv_integer(addr_in_row))(conv_integer(addr_in_col)+32) sram(conv_integer(addr_in_row))(conv_integer(addr_in_col)+16) sram(conv_integer(addr_in_row))(conv_integer(addr_in_col));end if;end if;end process;data_in = data;data = data_out when cs=0 and we = 1 else(others =Z);end Behavioral;仿真结果：写操作：读操作：仿真分析：在进行写操作时，片选信号低电平有效，we为0，在地址000001000存入0001；在进行读操作时，片选信号低电平有效，we为1，读出地址000001000中存入的数0001.实际框图：第五章‐实验（5%）简单程序中断方式接口电路的实现要求：按照P198，图5.41 实现一个简单的程序中断方式接口电路。VHDL代码：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use IEEE.STD_LOGIC_ARITH.ALL;entity shiyan5 is Port ( start : in STD_LOGIC;