HDL数字时钟设计.doc

河海大学计算机与信息学院（常州） 课程设计报告 题 目 实时时钟电路设计 专业、学号 通信工程0862310229 授课班号 275801 学生姓名 指导教师 奚 吉 完成时间 2010-1-6 课程设计 摘 要 【关键词】 ABSTRACT Digital Clock is a daily production of a very broad application items, the clock timing of the demand can be seen everywhere in society, they may have their own different look, but the principles are the same inside, and functions are the same, no almost outside the counting, timing, alarm chronograph, etc. still do. The curriculum requires QUARTUS 11 HDL language software to design a collection of the above-mentioned functions of the digital clock, and then through circuit board physical debugging. Digital clock design method has many kinds of small and medium scale integrated circuits can be composed of electronic clock; also use a dedicated clock chip and the required display circuit coupled with external circuit electronic clock; can also use the microcontroller to implement electronic bell and so on. These methods have their own characteristics. ????The digital clock design using Verilog HDL, a digital clock circuit, and 8 digital tube display. Is widely used Verilog hardware description language that can be used in the hardware design process, modeling, and simulation and other stages. Through this design allows students to enhance the understanding of HDL language to strengthen the practical application of QUARTUS 11 software, learn to use knowledge learned in class to solve the problem of the actual production and living, and effectively improve their professionalism and ability levels. 朗读 显示对应的拉丁字符的拼音 ? 字典 - 查看字典详细内容 【Key words】Digital clock Timing alarm 目录 一 系统的组成 ··················································5 二 软件流程图设计 ··················································6 三 程序模块设计 ··················································6 四 源程序设计 ··················································7 五 问题与调试 ·················································