低压低功耗电路设计.pptx
文本预览下载声明
A 10-bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First Successive Approximation;研究背景:ADCs能量利用率的提高使得传感器的节点应用到更严格的功耗限制环境,这些应用包括持续监测生命体征的医疗器件、机械振动和应变传感器、用于环境监测的温度传感器和化学传感器。将传感器信号数字化的可靠方法是使用一个恒定的采样率和分辨率,然而,由于存在干扰和信号本身的形状,使得许多传感器信号表现出速度和分辨率随时间变化的要求。
本文提出基于信号活跃性的节省功耗算法,称为最低有效位优先的逐次逼近,这样可以保持一个恒定的采样率和分辨率,从根本上避免了斜坡过载。;信号活跃性:;the LSB-first SA algorithm(最低有效位优先逐次逼近算法);当DIR=0时,DAC的输出电压 设置为D的下界,当DIR=1时,DAC的
输出电压 设置为D的上界。CMP=1时,说明 ,CMP=0时,
说明 。
;Fig 1. Example 10-bit conversions using the LSB-first SA algorithm.;Fig. 4. Simulated mean bitcycles/sample plotted against mean Δcode for fullscale sinusoid inputs of different frequencies. ;Fig. 5. Architecture of the LSB-first SAR ADC showing the main analog and digital blocks.;Fig. 7. Schematic of the two-stage dynamic comparator;The 10-bit ADC is implemented in 0.18 μm CMOS and occupies 0.12 mm .;In 0.6 V mode, the reduced gate drive voltage increases the sampling switch resistance, causing distortion which degrades the SNDR and SFDR near the Nyquist frequency (?奈奎斯特频率).;Δcode is low,resulting in lower P/fs.;A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating
SAR ADC With Adaptive Dynamic Range;研究背景:由于无线标准不断地往更大的带宽和更高的数据传输速度上发展,ADCs特必须跟上这日益发展的需求。如今,许多研究者从事于GSM, GPRS,LTE, GPS,WLAN等工作,要求ADCs的速度达到几十MS/s,8-10位的有效位,低功耗(尤其是在便携式设备,如手机)。而且,由于软件无线电(SDR)系统要求灵活的电路,这就要求ADCs应该具有全动态范围。
本文提出的variable-gain amplifier(VGA)-ADC组合能够满足这个要求,采样速度达到80MS/s,有效位达到9位。;Fig. 2. Traditional T/H and current integrating I/H.;Fig. 3. Operating principle of the VGA/ADC.;(top) HD3 vs. number of cells with I/H capacitance of 23 pF;(bottom) HD3 vs. I/H capacitance.;Fig. 5. Top-level VGA/ADC architecture.;Fig. 6. Transconductor schematic;Fig. 7. Amplification principle.;Fig. 9. I/H details;To further relax comparator noise requirements, the first nine comparisons are performed using a high-noise, low-power dynamic comparator and the two final comparisons are done using a lownoise,high-power comparator, w
显示全部