基于VHDL语言的数字频率计设计论文.doc

××大学本科生毕业设计 第 PAGE \* ROMAN IV 页 基于VHDL语言的数字频率计设计 摘 要 在电子技术中，频率是最基本的参数之一，并且与许多电参量的测量方案、测量结果都有十分密切的关系，因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速，以及便于实现测量过程自动化等优点，是频率测量的重要手段之一。本设计结合采用测频法与测周期法这两种频率测量方法，可以大大提高数字频率计的频带以及测量精度。 本设计采用模块化思想，将频率计的实现按功能分割成基准时间产生模块、高频计数模块、低频计数模块、数据处理模块、中央控制模块。其中，中央控制模块是整个系统的控制部分：高频信号采用测频法，直接在中央控制器显示输出；低频信号采用测周期法，由基准时间产生模块提供的计数时钟信号，再经过数据处理模块处理，在中央控制器模块上显示输出。各部分模块都采用超高速集成电路硬件描述语言（VHDL）来实现，所以尽管目标系统是硬件，但整个设计和修改过程如同完成软件设计一样方便和高效。 关键词：电子设计自动化;硬件描述语言;数字频率计 Design of a Digital Cymometer Based on VHDL Abstract In electronics, the frequency is one of the most basic parameters, and with many electrical parameters of the measurement program, measurement consequence of a very close relationship, so the frequency of measurement becomes very important. Measuring frequency of means, including electronic counter measuring frequency with high precision, easy to use, fast measurement and easy to realize the advantages of automated measurement process is an important means of frequency measurement. The design combination of frequency measurement method and the measurement cycle the two frequency measurement method can greatly enhance the digital frequency meter band and the measurement accuracy. The modular design ideas, the realization of the frequency counter divided by function into a reference time generator module, high frequency count module, low frequency count module, data processing module, the central control module. Among them, the central control module is part of the whole system of control: high-frequency signal with frequency measurement method, the direct display output in the central controller; low frequency signal by measuring cycle method, produced by the reference time clock module provides the count, and then through the data processing module processing, the central controller module display output. The part of the module is ultra high speed integrated circuit hardware description