江苏大学EDA课程设计实验报告.docx

EDA课程设计报告彩灯控制器的设计系统设计要求 ? 1、要有多种花型变化（至少设计4种）?2、多种花型可以自动变换，循环往复?3、彩灯变换的快慢节拍可以选择?4、具有清零开关系统设计方案根据系统设计要求，现设计一个具有六种花型循环变化的彩灯控制器。系统设计采用自顶向下的设计方法，系统的整体组转设计原理图如下图所示，它由时序控制模块和显示控制模块两部分组成。整个系统有3个输入信号：系统时钟信号CLK，系统清零信号CLR和控制彩灯节奏快慢的选择开关SPRRD。9个输出信号LED[8..0]，分别用于模拟彩灯。VHDL源程序（1）时序控制模块的VHDL源程序（sx.vhd）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SX ISPORT(SPEED : INSTD_LOGIC;CLK : INSTD_LOGIC;CLR : INSTD_LOGIC;CLK1 : OUTSTD_LOGIC);END SX;ARCHITECTURE ART OF SX ISSIGNAL CK : STD_LOGIC;BEGINPROCESS (CLK, CLR,SPEED)VARIABLE TEMP : STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINIF CLR=1 THEN CK=0; TEMP:=000;ELSIF (CLKEVENT AND CLK=1) THEN IF (SPEED=1)THEN IF TEMP=011 THEN TEMP:=000; CK=NOT CK; ELSE TEMP:=TEMP+1; END IF; ELSE IF TEMP=111 THEN TEMP:=000; CK=NOT CK; ELSE TEMP:=TEMP+1; END IF; END IF; END IF;END PROCESS;CLK1=CK;END ART;(2)显示控制模块的VHDL源程序（xs.vhd）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY XS ISPORT(CLK1 : INSTD_LOGIC;CLR : INSTD_LOGIC; LED: OUTSTD_LOGIC_VECTOR(8 downto 0));END entity XS;ARCHITECTURE ART OF XS IS TYPE STATE IS(S0,S1,S2,S3,S4,S5,S6);SIGNAL CURRENT_STATE: STATE;SIGNAL LIGHT: STD_LOGIC_VECTOR(8 DOWNTO 0); BEGINPROCESS (CLR, CLK1)ISCONSTANT L1:STD_LOGIC_VECTOR(8 DOWNTO 0):=001001001;CONSTANT L2:STD_LOGIC_VECTOR(8 DOWNTO 0):=010010010;CONSTANT L3:STD_LOGIC_VECTOR(8 DOWNTO 0):=011011011;CONSTANT L4:STD_LOGIC_VECTOR(8 DOWNTO 0):=100100100;CONSTANT L5:STD_LOGIC_VECTOR(8 DOWNTO 0):=101101101;CONSTANT L6:STD_LOGIC_VECTOR(8 DOWNTO 0):=110110110;BEGINIF CLR=1 THEN CURRENT_STATE=S0;ELSIF(CLK1EVENT AND CLK1=1) THEN CASE CURRENT_STATE IS WHEN S0 = LIGHT=ZZZZZZZZZ; CURRENT_STATE=S1; WHEN S1 = LIGHT=L1; CURRENT_STATE=S2; WHEN S2 = LIGHT=L2; CURRENT_STATE=S3; WHEN S3 = LIGHT=L3; CURRENT_STATE=S4; WHEN S4 = LIGHT=L4; CURRENT_STATE=S5; WHEN S5 = LIGHT=L5; CURRENT_STATE=S6; WHEN S6 = LIGHT=L6; CURRENT_STATE=S1; END CASE; END IF;END PROCESS;LED=LIGHT;END ARCHITECTURE ART;(3)彩灯控制器顶层设计的VHDL源程序（caideng.vhd）LIBRARY IEEE;USE