Intel英特尔GTS Interlaken IP 用户指南.pdf

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Altera®DesignHub

GTSInterlakenIPUserGuide

®

UpdatedforQuartusPrimeDesignSuite:25.1

IPVersion:7.0.0

OnlineVersion819200

SendFeedback2025.03.30

Contents

Contents

1.AbouttheGTSInterlakenIP3

1.1.GTSInterlakenIPFeatures3

1.2.GTSInterlakenIPDeviceFamilySupport4

1.3.DeviceSpeedGradeSupport5

1.4.GTSInterlakenIPPerformanceandResources5

1.5.GTSInterlakenIPRound-TripLatency6

1.6.GTSInterlakenIPReleaseInformation6

2.GettingStarted7

2.1.InstallingandLicensingIntelFPGAIPs7

2.1.1.IntelFPGAEvaluationMode7

2.2.GeneratedFileStructure9

2.3.SpecifyingtheGTSInterlakenIPParametersandOptions11

2.4.ReferenceandSystemPLLClockforYourIPDesign13

2.5.SimulatingtheGTSInterlakenIP13

2.6.CompilingtheFullDesignandProgrammingtheFPGA14

3.ParameterSettings15

3.1.AnalogParametersforGTSIPs16

4.FunctionalDescription19

4.1.DatapathFlow20

4.1.1.InterlakenTXPath21

4.1.2.InterlakenRXPath22

4.2.ModesofOperation25

4.2.1.InterleavedandPacketModes26

4.2.2.Multisegments31

4.3.Performance34

4.4.IPReset35

4.5.M20KECCSupport36

4.6.Out-of-BandFlowControl37

5.InterfaceSignals41

5.1.GTSInterlakenIPClockandResetInterfaceSignals41

5.2.GTSInterlakenIPTransmitUserInterfaceSignals42

5.3.GTSInterlakenIPReceiveUserInt