aug 3 sharc处理器内核体系结构-simd.pptx

UsingSIMDarchitectureeffectively

SIMDfeaturesExtensionto2106xarchitectureSIMDisaMODEofoperationWhenenableditaffectsdataaccessesaswellasamountofcomputationsperformedEachcomputeordataaccessinstructionisexecutedinbothprocessingelementsEachprocessingelementoperatesondifferentdataIncreasedPMandDMdatabuswidthsto64bitsEnablesfour32-bitdatawordstobetransferredeachcycle(2overeachbus)2

HowtoenableSIMD?SIMDmodecanbeenabledbysettingbit21(PEYEN)oftheMODE1register.FollowinginstructionenablesSIMDmode: bitsetmode1PEYEN;NOTE:theMODE1registerhasaonecycleeffectlatency3031210PEYEN=ProcessingElementYEnableorSIMDEnableBit0==PExenabledonly1==PExandPEyenabled

ComputationsandDataAccessOperations: SISDvsSIMDSIMDEnabled:Whenanycomputationordataaccessisexecuted,itwillbeperformedautomaticallyinbothprocessingelementsF0=F1+F2;explicitlydefinedinsourcecodeWillexecuteinPExS0=S1+S2;implicitoperationnotdefinedinsourcecodeWillbeautomaticallyexecutedinPEyinthesameinstructioncycleSIMDDisabled(SISDMode):OnlytheexplicitinstructionwillbeexecutedinPEx4

RegisterTransfersandSwaps

SISDvsSIMDR0=S4;SISD:transferoccursfromoneregistertoanotherSIMD:transferbetweenR0andS4inPExandsimaltaneoustransferbetweencomplimentaryregistersS0andR4inPEy5S4R0R4S0R0-S4;SwapbetweenadataregisterinPExandadataregisterinPEySwapOperationisthesameinSISDasinSIMD;noextraswapoperationoccursinSIMDmode.S4R0

DataaccessSIMDvsSISD

FactorsaffectingmemoryaccessesSINGLEORDUALACCESSSingleaccessr0=DM(i0,m0);Dualaccessr0=DM(i0,m0),r4=PM(i8,m8);ADDRESSSPACEShortWord,NormalWord,LongWordTheLW(Long-Word)instructionoptionprovides64-bitaccessinNormalWordspaceSISDVS.SIMDMode(enabledbyabitinMODE1)BROADCASTMode(enabledbyabitinMO