《动态扫描显示的数字时钟.doc

动态扫描显示的数字时钟 六进制计数器 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter6 is Port ( clk : in std_logic; reset : in std_logic; dout : out std_logic_vector(3 downto 0); c:out std_logic); end counter6; architecture Behavioral of counter6 is signal count : std_logic_vector(3 downto 0); begin dout = count; process(clk,reset) begin if reset= 0 then count = 0000; c=0; elsif rising_edge(clk) then if count=0101 then count=0000; c=1; else count=count+1; c=0; end if; end if; end process; end Behavioral; 十进制计数器 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter10 is Port ( clk : in std_logic; reset : in std_logic; dout : out std_logic_vector(3 downto 0); c:out std_logic); end counter10; architecture Behavioral of counter10 is signal count : std_logic_vector(3 downto 0); begin dout = count; process(clk,reset) begin if reset=0then count = 0000 ; c=0; elsif rising_edge(clk) then if count = 1001 then count = 0000; c=1; else count = count+1; c=0; end if; end if; end process; end Behavioral; 二十四进制计数器 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter24 is Port ( clk : in std_logic; reset : in std_logic; dout : out std_logic_vector(7 downto 0)); end counter24; architecture Behavioral of counter24 is signal count : std_logic_vector(7 downto 0); begin dout = count; process(clk,reset) begin if reset= 0 then count = elsif rising_edge(clk) then if count(3 downto 0)=1001 then count(3 downto 0)=0000; count(7 downto 4)=count(7 downto 4) +1; else count(3 downto 0)=count(3 downto 0)+1; end if; if countthen count end if; end if; end process; end Behavioral; 动态扫描显示 ibrary ieee; use ieee.std_logic_1164.all; entity clk1hz is port (clk : in std_logic; clk1hz :out std_logic); end clk1hz; architecture one of clk1hz is begin PROCESS(clk) variable cnt :