charge trap NAND flash.pdf

Charge-Trap NAND Flash Memory Souvik Mahapatra E E Dept, IIT Bombay, India C t ib ti S d C P Si h S G t K hitij A l kon r u ons: an ya , awan ng , uyog up a, s u uc , Piyush Dak, Sandeep Kasliwal, Udayan Ganguly, Dipankar Saha, Gautam Mukhopadhyay, Juzer Vasi 1Support: Applied Materials, Intel Corporation, SRC/GRC Outline FG NAND Flash scaling challenges SiN based charge trap flash – material dependence P/E simulation of SiN Flash Metal nanodot Flash Scalability simulation of m-ND Flash 2 NAND Flash Background BL DSL CG CD 15nm e l l s WL FG 50nm N o . o f c Figure: SamsungSL SSL TO 9nm L=35nm Memory state ?Electron transfer between substrate FG define memory state (write erase) ?FG surrounded by TO CD acts as electron storage well (non-volatility, need 10yrs), though leak out occurs over time (retention loss) 3 ?Repeated Write/Erase (10-100K needed) causes memory wear out (cycling endurance) NAND Flash Scaling ?More memory, faster access, reduced cost ?Guideline (ITRS roadmap): L=35nm (2009) CG CD 15nm , 28nm (2010/11), 22nm (2013/14)… SLC (1bit/ ll) MLC (2 3 bit / ll) f hi h TO 9nm FG 50nm ? ce , or s ce or g er density, higher reliability issuesL=35nm Scaling penalty: (1) Loss of CG – FG coupling (2) C ll t ll t lk Solution: Discrete trap- based charge storage e o ce cross a (3) Non-scaling of TO, FG and CD thickness CG CD, 12nm (4) Non-scaling of operating voltage TO, 6nm SiN, 6nm 4 (5) Higher reliability concern Planer CTF Devices test chip demonstrated (Samsung) ?Memory window close down with W/E cycling ?Data keeps leaking out (worse than FG!) ?Loss of memory ti 5 opera on CTF reliability worse than FG, no product yet Retention Issue Lateral or Vertical charge migration Trap depth of SiN is key to control charge migration 6 Solution – to cut SiN above STI (Samsung, 2007) NAND 3D Memory 3D CTF proposed as a way to move forward below 20nm node: BiCs (Toshiba), TCAT (Samsung) 7 Motivation CT