HDMI接口设备与线缆技术简介.ppt

Call flow when echo 0 sys/devices/platform/omapdss/display*/enabled Is called hdmi_disable_display Disabled the dss_clk requested by HDMI. Hdmi_enable_clocks(0). Sets the power state of the HDMI PLL block to ALL_OFF HDMI_W1_SetWaitPllPwrState Set the PHY block to off hdmi_phy_off GPIO configurations are pulled down. References TI OMAP4 TRM /general/docs/wtbu/wtbudocumentcenter.tsp?templateId=6123navigationId=12667 HDMI 1.3 specification /learningcenter/faq.aspx EDID information /wiki/Extended_display_identification_data /learningcenter/presentations.aspx (Implementing EDID that works) Connector http://pinouts.ru/Video/hdmi_pinout.shtml * DDC Display Data Channel (HDMI) transmitter A device with an HDMI output. (HDMI) receiver A device with an HDMI input. TMDS clock is used by the receiver as a frequency reference for data recovery on the three TMDS data channels. * * * * Diagram from http://pinouts.ru/Video/hdmi_pinout.shtml * * The transmitter shall not transmit at TMDS clock rates higher than the maximum rate supported by the receiver, as determined by video format and Deep Color mode support indications but limited by the Max_TMDS_Clock field of the HDMI VSDB. Deep Color Pixel Packing For a color depth of 24 bits/pixel, pixels are carried at a rate of one pixel per TMDS clock. At deeper color depths, the TMDS clock is run faster than the transmitter pixel clock providing the extra bandwidth for the additional bits. The TMDS clock rate is increased by the ratio of the pixel size to 24 bits: ? 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) ? 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) ? 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) ? 48 bit mode: TMDS clock = 2.0 x pixel clock (2:1) * * * * * * * HDMI 接口设备与线缆技术简介 HDMI Members HDMI Switch HDMI Repeater HDMI Splitter HDMI DVI Adaptors Cable HDMI to HDMI, ( Economic type) HDMI to HDMI with Weave HDMI to HDMI with Weave Strip HDMI to DVI , ( Economic type) Wall Pla