ultimate scaling of high-κ gate dielectrics higher-κ or interfacial layer scavenging最终缩放high-κ门电介质higher-κ或界面层清除.pdf

Materials 2012, 5, 478-500; doi:10.3390/ma5030478 OPEN ACCESS materials ISSN 1996-1944 /journal/materials Review Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging? Takashi Ando IBM Thomas J. Watson Research Center, Yorktown Heights, New York, NY 10598, USA; E-Mail: andot@; Tel.: +1-914-945-1738; Fax: +1-914-945-4184 Received: 29 January 2012; in revised form: 11 February 2012 / Accepted: 6 March 2012 / Published: 14 March 2012 Abstract: Current status and challenges of aggressive equivalent-oxide-thickness (EOT) scaling of high-κ gate dielectrics via higher-κ (20) materials and interfacial layer (IL) scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm), but with effective workfunction (EWF) values suitable only for n-type field-effect-transistor (FET). Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL) is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly