基于FPGA的DPSK信号产生器的设计详解.doc

基于FPGA的2DPSK信号产生器的设计 摘 要： 随着时代的进步，FPGA的应用也越来越广泛，FPGA用硬件描述语言（Verilog HDL）来实现2DPSK信号的调制系统，不仅简单方便，而且还能满足现代设备快速、准确、功耗低的特点。Verilog语言有着灵活多样的电路描述风格，语言功能性强，并且简单易学，这些优良的性能使其得到广泛流行。数字通信技术与FPGA的结合是现代通信系统发展的一个必然趋势。FPGA实现2DPSK信号可用如下方法，先通过FPGA产生时钟信号，经过分频器产生两路时钟，一路用于基带码的产生，也就是用于驱动M序列信号发生器产生绝对码，另一路用于采样正弦信号。M序列产生的绝对码经过差分运算转换成相对码，再把相对码加到正弦信号上输出，这就相当于对原码进行了调相输出。而FPGA只能处理数字信号，因此要经过DAC器件转换为模拟信号，从而产生2DPSK信号。通过对仿真波形的分析可知，该方案很好的实现了2DPSK信号产生器的功能。 关键词：FPGA；Verilog HDL；2DPSK信号产生器；数字调制；串并转换； Design of 2DPSK Signal Generator Based on FPGA Abstract： With the progress of the times, FPGA is used more and more popularly. FPGA used hardware description language ( Verilog HDL ) to achieve the 2DPSK signal modulation systemIts not only simple and convenient, but also equipped with many excellent characteristics of modern devices, such as fast, accurate, low power consumption. Verilog language can descript circuit variously and flexibly, and has powerful function. What’s more, it’s easy to learn for us. These excellent properties make Verilog language applied widely. The combination of digital communication technology and FPGA is a certainly trend of the development of modern communication system. The process of producing 2DPSK signal by FPGA is as follows. The clock signal generated by FPGA will generate two signals with different frequency. One is used to sampling, the other is to drive M array signal generator. It will be converted to absolute code, and be used to modulate. Because only the digital signal can be processed by FPGA, DAC is needed to generate 2DPSK signal. Key words：FPGA；Verilog HDL；2DPSK signal generator；digital modulation； 目 录 1 绪 论 3 2 应用软件及器件介绍 4 2.1 信号发生器简介 4 2.2 EDA技术简介 4 2.3 FPGA和CPLD器件简介 5 2.4 Verilog HDL简介 6 2.5 Quartus II简介 7 3 2DPSK信号产生器的设计 8 3.1 2DPSK信号产生器的基本原理 8 3.1.1 2DPSK信号原理 8 3.1.2 设计思路及方法 9 3.2 软件设计 10 3.2.1 分频器 10 3.2.2 M序列产生器 11 3.2.3 差分运算 12 3.2.4 选相调制 12 3.2.5 正弦信号发生器 13 3.2.6 2DPSK信号波形仿真 14 3.3 硬件设计 15 3.3.1 器件说明 16 3.3.2 并行输入方式设计 19 3.3